K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, M. Yotsuyanagi
{"title":"A CMOS 50% duty cycle repeater using complementary phase blending","authors":"K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, M. Yotsuyanagi","doi":"10.1109/VLSIC.2000.852847","DOIUrl":null,"url":null,"abstract":"The authors report a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"54 6 1","pages":"48-49"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"52","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852847","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 52
Abstract
The authors report a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.