2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)最新文献

{"title":"Study on copper plating solutions for fast filling of through silicon via (TSV) in 3D electronic packaging","authors":"H. Wu, S. Lee","doi":"10.1109/IMPACT.2011.6117173","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117173","url":null,"abstract":"Copper electrodeposition in acidic cupric methanesulfonate electrolyte with organic additives was discussed in this study. The influence of the additives in acidic cupric methanesulfonate bath was studied by means of electrochemical measurement using a rotary electrode and actual TSV copper depositions. The electrochemical parameters including exchange current density and cathodic transfer coefficient of base cupric methanesulfonate electrolyte were successfully determined. Chronoamperometry (CA) was conducted to verify the diffusion time of additives to the surface of electrodes and the corresponding diffusion constants were characterized.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"54 1","pages":"343-346"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91172871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"International microsystems, packaging, assembly and circuits technology conference (IMPACT 2011): P1. Emerging systems packaging technologies","authors":"T. Hofmann, S. Gottschling, B. Schuch, A. Neumann","doi":"10.1109/IMPACT.2011.6117178","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117178","url":null,"abstract":"The future challenges for electronic printed circuit boards in automotive applications is further miniaturization, while increasing reliability and reducing costs. Conventional approaches are limited by the latest circuit substrate requirements. Therefore innovative integration concepts and packaging technologies must be evaluated. For this purpose, Continental has managed VISA, a three-year project funded by the Federal Ministry for Education and Research, where electronic components are embedded into PCBs. The so-called i²Board concept was favourized, developed by Schweizer Electronic AG, in which active and/or passive components are mounted and connected onto an electrical substrate material comparable to a flex foil and already can be functionally tested. Afterwards, the assembly is embedded between the inner layers of the PCB and integrated into the PCB´s set up. Successful developments were conducted with regard to novel ferrite materials for the embedding of inductivities. Also results for bare dies embedded with new connection technologies, e.g. Cu-pillar-bumping for application for transmission control units are outlined","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"15 1","pages":"291-293"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80631083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A numerical prediction of wire crossover applying to microchip encapsulation","authors":"Y. Chou, H. Chiu, Jyh-Jer Jwo","doi":"10.1109/IMPACT.2011.6117244","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117244","url":null,"abstract":"Microchip encapsulation is of dominance in the packaging of Plastic-Encapsulated Microelectronics (PEM). During fabrication of the encapsulation, the sweep deflection of wire bond caused by compound flows obviously results in wire crossover and shorting. Thereby, it is necessary to understand mechanical behaviors of the wire sweep, while it is critical that reduction of the sweep yields clearance of sufficient space between wires. As a rule, a position of a wire with the largest Wire Sweep Index (WSI) possesses the highest possibility of the wire crossover. Recent advances of the encapsulation technologies tend toward smaller scale and higher density, wherein the wire crossover is observed with difficulty. To date, the Computer-Aided Engineering (CAE) technologies have been preferably used in viewing positions of wire crossover. Using the CAE technology, the primary objective of this paper is to develop a useful tool to connect pre-process, filling and structure analyses and post-process, which gives a comprehensive solution for microchip encapsulation. In particular, the wire sweep phenomenon inside the package is found. Furthermore, the CAE users can check the possibility of wire crossover under any processing condition. Thus, application of the CAE technology significantly introducing to mold design for microchip encapsulation is feasible with high reliability.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"1 1","pages":"165-168"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86841497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Nickel solder ball performance for Pb-free LFBGA assembly under oxygenous reflow","authors":"Tien-Tsorng Shih, Wei-Chih Chen, Win-Der Lee, Mu-Chun Wang","doi":"10.1109/IMPACT.2011.6117250","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117250","url":null,"abstract":"Due to the technology improvement of ball-grid-array (BGA) package, the high-pin count concept was derived to the mass production. The low profile fine pitch BGA (LFBGA) package was employed to gain the assembly competition. The smaller diameter of solder ball, 0.3 mm, must be incorporated and the composition of solder ball needs to be modified such as including nickel to strengthen the adhesion capability in IMC layer. Since the oxygen concentration in flow process usually works upon the quality of solder joint such as oxidation causing aged effect and quality of inter-metal compound, the oxygen variance is checked in this study. Furthermore, the flux as solder assistance is also a cardinal factor affecting the solder adherence between LFBGA substrate and solder ball. Adopting the temperature cycling test, shear test and drop test to understand the adhesion ability for lead-free solder balls on LFBGA substrate assisted with several fluxes, the optimal process recipe was obtained. The soldering performance was promoted well.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"10 1","pages":"439-442"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84407575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Estimation for equivalent thermal conductivity of silicon-through vias TSVs used for 3D IC integration","authors":"H. Chien, J. Lau, Y. Chao, R. Tain, M. Dai, W. Lo, M. Kao","doi":"10.1109/IMPACT.2011.6117240","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117240","url":null,"abstract":"In this study, thermal performance of 3D IC integration is investigated. Emphasis is placed on the determination of a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches, TSV thicknesses, passivation thicknesses, and microbump pads. Also, a slice model to imitate a 3D memory stacked chip is adopted to verify the accuracy of the equivalent equations. Finally, the feasibility of these equivalent equations is demonstrated through a simple 3D IC integration structure.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"77 1","pages":"153-156"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83341340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel FR-4 material for embedded substrate","authors":"C. Hong, Ming C. Lee","doi":"10.1109/IMPACT.2011.6117237","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117237","url":null,"abstract":"Two processes of components embedding, both active dies and passive components, have been demonstrated so far — one is the embedding of chip by ABF/RCC material, and the other is the embedding by multiple plies of prepreg with machined cavity of placing component. ABF/RCC materials appear to the most straight forward way to embed components into PCB. The drawback is that the components to be embedded have to be thinned to 50μm but this is not practical for all types of components, and also the cost is very high. Multiple-ply prepreg with machined cavity can accommodate die of various thickness and thus offer more choice of different component thickness. However they do not get wide acceptance because of the low throughput and the concerns over the yield. To address the problem component embedding and offer the solution, Atotech has developed a novel process of manufacturing FR-4 material. This novel process, named “Advanced Dielectric Epoxy Powder Technology (ADEPT)”, is a solvent-free production technology. The dielectric is made of powder and is later coated on the copper foil. The final form is a resin-coated copper foil (RCC.) Moreover, the glass fabric can be laminated into the RCC, making it a Reinforced Resin-Coated Copper foil (RRCC.) The materials have passed reliability tests required in PCB and assembly industry, which include lead-free assembly, MSL, HAST, CAF, and TCT. By ADEPT, a multi-layer material, in sheet form, can be produced for the embedded substrate. First, a reinforced dielectric layer with glass fabric will offer good dimension control. Second, an additional resin layer, with high filler content to reduce CTE, will be used for component embedding. With the multi-layer material, the process of component embedding can be done in one go, without having the drawbacks of the large warpage by ABF, or the step of the cavity formation required by multiple-ply prepreg. After component embedding, the reinforced layer effectively minimizes the warpage so the panel can be laser drilled and processed. Finally an ultra thin, low profile copper foil will be ideal for modified Semi-Additive Process (mSAP), a way of fine line structuring at relatively low cost. Since by ADEPT the dielectric is made of powder, it soon lends itself easily to the molding process in assembly. Its advantages over molding compounds are the capabilities of form small (50μm) laser vias due to the selection of sub-micron filler (Max./Mean filler size=1.0/0.3μm) and it is compatible with e'less copper deposition. As close partners, Atotech and ASE Global are exploring the applications of this dielectric powder as a molding compound for component embedding process.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"2 1","pages":"177-178"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74913773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ratcheting and creep responses of SAC solder joints under cyclic loading","authors":"Li-Ying Hsieh, H. Yang, T. Chiu","doi":"10.1109/IMPACT.2011.6117276","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117276","url":null,"abstract":"To investigate the fatigue response of Pb-free Sn3.8Ag0.7Cu (SAC3807) solder, cyclic double lap shear tests consisting both loading ramp and dwell periods under isothermal conditions were performed on ball grid array (BGA) SAC3807 solder joints. Factors including test temperature, shear load amplitude and load dwell time were considered in the experiment for determining the damage acceleration effects. From the experiment it was observed that, during the cyclic shear load ramping stages, ratcheting still occurs even though the peak load is below the yielding point of solder. Transient and steady-state creep responses were also observed during the dwell stages of the cycling profile. Both ratcheting and creep responses become more significant as temperature and peak load increases. An important finding of the study is that the contribution of creep to the overall load-displacement hysteresis is more significant than the contribution of ratcheting. The corresponding inelastic energy dissipation under the cyclic double lap shear experiments were compared numerically to that of a typical wafer-level package under board-level temperature cycling (T/C). The comparison can be used for developing acceleration factors between the cyclic shear and board-level T/C tests.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"56 1","pages":"96-99"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76050856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New PC board structure for power supply technology over GHz frequency verificated with 32bit SSN driver system","authors":"Norifumi Sasaoka, Takafumi Ochi, Y. Akiyama, K. Kono, C. Ueda, K. Otsuka","doi":"10.1109/IMPACT.2011.6117167","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117167","url":null,"abstract":"Power integrity (pi) for recent electronics circuits and systems is the most emergent technology in the GHz clock field and has been addressed in important papers through several approaches[1][2]. The latest concept of the best pi condition is recognized as maintaining lower impedance between power and ground lines or planes without any clock frequency dependency, even in the GHz region. We found this concept in a relatively old book [3] from the 1980s; thus, it is not the latest idea. However, it cannot be completely realized by the several previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that plane power and ground resonance are induced electromagnetic interference (emi) problems due to resonance caused by eddy currents or multiple reflections of voltage fluctuations. a novel technology was used in our previous study only using a conductive layer of dispersed metal particles [4]. The structure is consisted of a conventional fr-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer [4]. This structure improved the pi for any clock frequency especially in GHz region with an impedance of less than 1 Ω. This improvement is verified by an actual 16bit (two set) 3 Gbps/pin i/o interface board in this study. Even though the simultaneous switching of 32 drivers gave a fairly high current slew-rate of (8 mA × 32) / 60 ps = 4.27 × 109 A/s, the pi status was kept at an excellent value within 10% of the Vdd fluctuation.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"2013 1","pages":"55-58"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87995363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fault-tolerant mesh for 3D network on chip","authors":"Kai-Yang Hsieh, Bo-Chuan Cheng, Ruei-Ting Gu, Katherine Shu-Min Li","doi":"10.1109/IMPACT.2011.6117292","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117292","url":null,"abstract":"3D Mesh NoCs (Network on Chips) are one of the best approaches to solve the complexity of interconnect structures in SoCs (System on Chips) which leads to lower yield. In this paper, we present a Mesh-based scheme for 3D NoCs with fault-tolerance that helps increasing chips' reliability and yield. There are several phases for this scheme. The phase I transforms a 2D NoC into an optimized 3D NoC under the constraints of area, routing length, temperature, performance and etc. Then, we optimize the I/O placement to get the best routing between I/O pads and all cores by clustering the placement of each core and reassign the tier sequence to minimize the number of TSVs. Finally, we build up the Mesh topology for each tier with squaring the maximum number of cores. For example, we need a 4×4 Mesh if the maximum cores in each tier are 15. Once the 3D Mesh topology is ready, we are going to set up the routing scheme that provides the minimum number of routers and the minimum routing latency in phase II. We also have a routing scheme to control the data flow and distribute the communication overhead. Phase III is to search the replacement routing paths. There will be at least 2 paths for each connection. The more replacement paths we found, the more faults can be tolerated and more computing time will be needed. We verify the fault-tolerant 3D Mesh NoC in phase IV. First, we randomly insert some faults to verify if the NoC is still working. We can get the maximum number of faults to be tolerated by increasing the number of faults until the system crash in the second step. The verification may need hundreds of times to get the approximate maximum faults. If the fault toleration is not good enough, we can go back to phase III to search more replacements. Experimental results show to this verified fault-tolerant 3D Mesh scheme to be effective and efficient. This scheme can efficiently transform a complex 2D NoC into 3D fault-tolerant Mesh NoC according to the user-defined constraints and also provides the tradeoff analysis between the tolerance and the search time of the effective replacement paths.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"1 1","pages":"202-205"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82809550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electroless nickel/Immersion gold process on Aluminum alloy electrodes","authors":"S. Kawashima","doi":"10.1109/IMPACT.2011.6117175","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117175","url":null,"abstract":"Electronic equipment has changed to have higher performance with minimized in size. This trend required to electronic devices minimization also. Numerous packaging techniques have developed using metal flame, PWB material and plastic tape to mount semiconductor devices on PWB1). To achieve further high mounting density, the semiconductor device directly solder mounted on package after forming metal bumps on electrode of semiconductor devices. Aluminum alloy is common material for electrode of semiconductor devices, since it has relatively high conductivity, chemically stable and less reaction in semiconductor manufacturing process. However, it needs other meal layer for soldering to form bump on it. Sputtered Ti/Cu layer and electrolytic solder plating is widely used to form solder bump. However, this process requires longer and costly process such as multiple vacuum process, photo image process, etc.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"36 1","pages":"381-384"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85465008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}