2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)最新文献

{"title":"Solder stability for Pb-free HBGA assembly with oxygenous reflow","authors":"Tien-Tsorng Shih, Wei-Chih Chen, Win-Der Lee, Mu-Chun Wang","doi":"10.1109/IMPACT.2011.6117249","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117249","url":null,"abstract":"In ball-grid-array (BGA) package technology, the oxygen concentration in flow process predominantly influences the quality of solder conjunction such as oxidation causing aged effect and quality of inter-metallic compound. In addition, the flux as solder assistance is also a key factor determining the solder adhesion ability between carrier HBGA substrate and solder ball. Using the temperature cycling test, shear test and drop test to distinguish the adhesion ability for lead-free solder balls on HBGA substrate assisted with several fluxes, the optimal process recipe was achieved. The soldering performance was impressive.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"81 1","pages":"435-438"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78658923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low temperature bonding of 30um pitch micro bump interconnection for 3D IC stacking using non-conductive adhesive","authors":"Yu-Min Lin, C. Zhan, Yu-wei Huang, Su-Ching Chung, Chia-Wen Fan, Su-Mei Chen, Yu-lan Lu, Tai-Hong Chen","doi":"10.1109/IMPACT.2011.6117284","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117284","url":null,"abstract":"For evaluating the feasibility of adhesive bonding by NCF (non-conductive film) in micro bump joints, three types of micro joints were adopted in this study. The structure of the type I micro joints was Cu/Ni/Au while that of the type II micro joints was Cu/Ni/Au micro bump joined with Cu/Sn solder micro bump. Both the type I and type II micro joint were bonded by using NCF. The structure of the type III micro joints were the same, but the type III micro joints were produced by eutectic bonding. For the type III micro joints, the micro gap between chips was wrapped by a capillary underfill. The bonding results revealed that the contact resistance of the NCF joints was in the range of 100 Qm ∼ 400 Qm which was higher than that of eutectic joints. Electrical continuity of micro bump interconnection was monitored by measuring the contact resistance of four-point Kelvin structure and daisy chain during reliability test. Thermal cycling test and thermal humidity storage test were conducted to evaluate the reliability performance of these three types of micro interconnections. The reliability test displayed that the reliability performance of eutectic joints was better than that of the NCF joints. The study showed that NCF joints have great potential to be applied in low temperature bonding of fine pitch 3D IC stacking.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"24 14 1","pages":"478-481"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89187641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A numerical prediction of wire crossover applying to microchip encapsulation","authors":"Y. Chou, H. Chiu, Jyh-Jer Jwo","doi":"10.1109/IMPACT.2011.6117244","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117244","url":null,"abstract":"Microchip encapsulation is of dominance in the packaging of Plastic-Encapsulated Microelectronics (PEM). During fabrication of the encapsulation, the sweep deflection of wire bond caused by compound flows obviously results in wire crossover and shorting. Thereby, it is necessary to understand mechanical behaviors of the wire sweep, while it is critical that reduction of the sweep yields clearance of sufficient space between wires. As a rule, a position of a wire with the largest Wire Sweep Index (WSI) possesses the highest possibility of the wire crossover. Recent advances of the encapsulation technologies tend toward smaller scale and higher density, wherein the wire crossover is observed with difficulty. To date, the Computer-Aided Engineering (CAE) technologies have been preferably used in viewing positions of wire crossover. Using the CAE technology, the primary objective of this paper is to develop a useful tool to connect pre-process, filling and structure analyses and post-process, which gives a comprehensive solution for microchip encapsulation. In particular, the wire sweep phenomenon inside the package is found. Furthermore, the CAE users can check the possibility of wire crossover under any processing condition. Thus, application of the CAE technology significantly introducing to mold design for microchip encapsulation is feasible with high reliability.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"1 1","pages":"165-168"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86841497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on copper plating solutions for fast filling of through silicon via (TSV) in 3D electronic packaging","authors":"H. Wu, S. Lee","doi":"10.1109/IMPACT.2011.6117173","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117173","url":null,"abstract":"Copper electrodeposition in acidic cupric methanesulfonate electrolyte with organic additives was discussed in this study. The influence of the additives in acidic cupric methanesulfonate bath was studied by means of electrochemical measurement using a rotary electrode and actual TSV copper depositions. The electrochemical parameters including exchange current density and cathodic transfer coefficient of base cupric methanesulfonate electrolyte were successfully determined. Chronoamperometry (CA) was conducted to verify the diffusion time of additives to the surface of electrodes and the corresponding diffusion constants were characterized.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"54 1","pages":"343-346"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91172871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and implementation of 3D-thermal test chip for exploration of package effects","authors":"Jui-Hung Chien, C. Lung, Ta‐Wei Lin, Kun-Ju Tsai, Ting-Sheng Chen, Yung-Fa Chou, Ping-Hei Chen, Shih-Chieh Chang, D. Kwai","doi":"10.1109/IMPACT.2011.6117289","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117289","url":null,"abstract":"Thermal solution and thermal management are critical issues in either 2.5D or 3D stacking design, especially when the hotspots are not located next to the heat sink. On the other hand, chip and package designers are eager to know the realtime temperature performance of the stacked chips therefore the workload can be assigned to the proper domain. Hence, a thermal test chip for evaluating the package is proposed in this paper. The thermal sensor network based on a ring oscillator is implemented in this work. Infrared radiation microscopic is employed for inspecting the real-time temperature performance of the chip and package. Four types of package are implemented and experimented by inspection of infrared radiation thermography. The experimental results show that one of proposed design provides good temperature consistency within difference of 0.6°C with the thermal sensors. Meanwhile, the proposed package has excellent capability for evaluating thermal management of the stacked dies by providing good thermal non-uniformity by 0.035 °C/mm.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"42 1","pages":"238-241"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91039421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ratcheting and creep responses of SAC solder joints under cyclic loading","authors":"Li-Ying Hsieh, H. Yang, T. Chiu","doi":"10.1109/IMPACT.2011.6117276","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117276","url":null,"abstract":"To investigate the fatigue response of Pb-free Sn3.8Ag0.7Cu (SAC3807) solder, cyclic double lap shear tests consisting both loading ramp and dwell periods under isothermal conditions were performed on ball grid array (BGA) SAC3807 solder joints. Factors including test temperature, shear load amplitude and load dwell time were considered in the experiment for determining the damage acceleration effects. From the experiment it was observed that, during the cyclic shear load ramping stages, ratcheting still occurs even though the peak load is below the yielding point of solder. Transient and steady-state creep responses were also observed during the dwell stages of the cycling profile. Both ratcheting and creep responses become more significant as temperature and peak load increases. An important finding of the study is that the contribution of creep to the overall load-displacement hysteresis is more significant than the contribution of ratcheting. The corresponding inelastic energy dissipation under the cyclic double lap shear experiments were compared numerically to that of a typical wafer-level package under board-level temperature cycling (T/C). The comparison can be used for developing acceleration factors between the cyclic shear and board-level T/C tests.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"56 1","pages":"96-99"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76050856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel FR-4 material for embedded substrate","authors":"C. Hong, Ming C. Lee","doi":"10.1109/IMPACT.2011.6117237","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117237","url":null,"abstract":"Two processes of components embedding, both active dies and passive components, have been demonstrated so far — one is the embedding of chip by ABF/RCC material, and the other is the embedding by multiple plies of prepreg with machined cavity of placing component. ABF/RCC materials appear to the most straight forward way to embed components into PCB. The drawback is that the components to be embedded have to be thinned to 50μm but this is not practical for all types of components, and also the cost is very high. Multiple-ply prepreg with machined cavity can accommodate die of various thickness and thus offer more choice of different component thickness. However they do not get wide acceptance because of the low throughput and the concerns over the yield. To address the problem component embedding and offer the solution, Atotech has developed a novel process of manufacturing FR-4 material. This novel process, named “Advanced Dielectric Epoxy Powder Technology (ADEPT)”, is a solvent-free production technology. The dielectric is made of powder and is later coated on the copper foil. The final form is a resin-coated copper foil (RCC.) Moreover, the glass fabric can be laminated into the RCC, making it a Reinforced Resin-Coated Copper foil (RRCC.) The materials have passed reliability tests required in PCB and assembly industry, which include lead-free assembly, MSL, HAST, CAF, and TCT. By ADEPT, a multi-layer material, in sheet form, can be produced for the embedded substrate. First, a reinforced dielectric layer with glass fabric will offer good dimension control. Second, an additional resin layer, with high filler content to reduce CTE, will be used for component embedding. With the multi-layer material, the process of component embedding can be done in one go, without having the drawbacks of the large warpage by ABF, or the step of the cavity formation required by multiple-ply prepreg. After component embedding, the reinforced layer effectively minimizes the warpage so the panel can be laser drilled and processed. Finally an ultra thin, low profile copper foil will be ideal for modified Semi-Additive Process (mSAP), a way of fine line structuring at relatively low cost. Since by ADEPT the dielectric is made of powder, it soon lends itself easily to the molding process in assembly. Its advantages over molding compounds are the capabilities of form small (50μm) laser vias due to the selection of sub-micron filler (Max./Mean filler size=1.0/0.3μm) and it is compatible with e'less copper deposition. As close partners, Atotech and ASE Global are exploring the applications of this dielectric powder as a molding compound for component embedding process.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"2 1","pages":"177-178"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74913773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Annealing effect of niobium pentoxide for low voltage electrowetting on dielectric (EWOD)","authors":"Hsiu-Hsiang Chen, C. Fu","doi":"10.1109/IMPACT.2011.6117208","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117208","url":null,"abstract":"In this paper, the high dielectric constants for Nb2O5 (∼25.5) were deposited by a RF reactive magnetron sputtering and respectively annealed at 400 °C O2 ambiance for 30 min in a conventional furnace. Based on the results, an electrowetting optical deflector (EOD) filled with the water (1% sodium dodecyl sulfate (SDS)) and dodecane was fabricated and tested, and the contact angle of the inclined liquid surface on the left and right sidewall can be varied about 70° at 9 V operating voltage. This study provides a practical way to fabricate a high dielectric constant layer for low voltage electrowetting on dielectric (EWOD) application.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"50 1","pages":"401-403"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77549900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of underfill material for fine pitch Cu pillar bump","authors":"Huei-Nuan Huang, Yi-Chian Liao, Wen-Tsung Tseng, Chun-Tang Lin, Chi-Hsin Chiu","doi":"10.1109/IMPACT.2011.6117231","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117231","url":null,"abstract":"Underfill (UF) is an important process in flip-chip packaging because of significant impact on the reliability of the IC's package. For three-dimensional integrated circuit (3DIC) demand, fin e pit ch an d fine gap are the market trend in the future due to t he requirements of functionality and performance in electronic device. In this study, a two die stacking, with Cu pillar bumps area of multiple pitches, joint by thermal-compress ion bon ding without flux has been demonstrated in chip on chip fashion. The maximum standoff height after micro bump joint is less than 25 um. Because of different pitch and fine gap structure, underfill dispensing becomes a challenge process for 3DIC stacking. Two different types of underfill were chosen to study in this paper. UF-A has higher viscosity and better stress simulation than UF-B. Different dispensing design were also studied in this paper, and the mechanism of underfill flowing property was determined by scanning acoustic tomograph (SAT) for comparing the effect of dispensing parameter and material.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"60 1","pages":"150-152"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84475220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fault-tolerant mesh for 3D network on chip","authors":"Kai-Yang Hsieh, Bo-Chuan Cheng, Ruei-Ting Gu, Katherine Shu-Min Li","doi":"10.1109/IMPACT.2011.6117292","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117292","url":null,"abstract":"3D Mesh NoCs (Network on Chips) are one of the best approaches to solve the complexity of interconnect structures in SoCs (System on Chips) which leads to lower yield. In this paper, we present a Mesh-based scheme for 3D NoCs with fault-tolerance that helps increasing chips' reliability and yield. There are several phases for this scheme. The phase I transforms a 2D NoC into an optimized 3D NoC under the constraints of area, routing length, temperature, performance and etc. Then, we optimize the I/O placement to get the best routing between I/O pads and all cores by clustering the placement of each core and reassign the tier sequence to minimize the number of TSVs. Finally, we build up the Mesh topology for each tier with squaring the maximum number of cores. For example, we need a 4×4 Mesh if the maximum cores in each tier are 15. Once the 3D Mesh topology is ready, we are going to set up the routing scheme that provides the minimum number of routers and the minimum routing latency in phase II. We also have a routing scheme to control the data flow and distribute the communication overhead. Phase III is to search the replacement routing paths. There will be at least 2 paths for each connection. The more replacement paths we found, the more faults can be tolerated and more computing time will be needed. We verify the fault-tolerant 3D Mesh NoC in phase IV. First, we randomly insert some faults to verify if the NoC is still working. We can get the maximum number of faults to be tolerated by increasing the number of faults until the system crash in the second step. The verification may need hundreds of times to get the approximate maximum faults. If the fault toleration is not good enough, we can go back to phase III to search more replacements. Experimental results show to this verified fault-tolerant 3D Mesh scheme to be effective and efficient. This scheme can efficiently transform a complex 2D NoC into 3D fault-tolerant Mesh NoC according to the user-defined constraints and also provides the tradeoff analysis between the tolerance and the search time of the effective replacement paths.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"1 1","pages":"202-205"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82809550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}