2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)最新文献

{"title":"Study on copper plating solutions for fast filling of through silicon via (TSV) in 3D electronic packaging","authors":"H. Wu, S. Lee","doi":"10.1109/IMPACT.2011.6117173","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117173","url":null,"abstract":"Copper electrodeposition in acidic cupric methanesulfonate electrolyte with organic additives was discussed in this study. The influence of the additives in acidic cupric methanesulfonate bath was studied by means of electrochemical measurement using a rotary electrode and actual TSV copper depositions. The electrochemical parameters including exchange current density and cathodic transfer coefficient of base cupric methanesulfonate electrolyte were successfully determined. Chronoamperometry (CA) was conducted to verify the diffusion time of additives to the surface of electrodes and the corresponding diffusion constants were characterized.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"54 1","pages":"343-346"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91172871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"International microsystems, packaging, assembly and circuits technology conference (IMPACT 2011): P1. Emerging systems packaging technologies","authors":"T. Hofmann, S. Gottschling, B. Schuch, A. Neumann","doi":"10.1109/IMPACT.2011.6117178","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117178","url":null,"abstract":"The future challenges for electronic printed circuit boards in automotive applications is further miniaturization, while increasing reliability and reducing costs. Conventional approaches are limited by the latest circuit substrate requirements. Therefore innovative integration concepts and packaging technologies must be evaluated. For this purpose, Continental has managed VISA, a three-year project funded by the Federal Ministry for Education and Research, where electronic components are embedded into PCBs. The so-called i²Board concept was favourized, developed by Schweizer Electronic AG, in which active and/or passive components are mounted and connected onto an electrical substrate material comparable to a flex foil and already can be functionally tested. Afterwards, the assembly is embedded between the inner layers of the PCB and integrated into the PCB´s set up. Successful developments were conducted with regard to novel ferrite materials for the embedding of inductivities. Also results for bare dies embedded with new connection technologies, e.g. Cu-pillar-bumping for application for transmission control units are outlined","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"15 1","pages":"291-293"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80631083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A numerical prediction of wire crossover applying to microchip encapsulation","authors":"Y. Chou, H. Chiu, Jyh-Jer Jwo","doi":"10.1109/IMPACT.2011.6117244","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117244","url":null,"abstract":"Microchip encapsulation is of dominance in the packaging of Plastic-Encapsulated Microelectronics (PEM). During fabrication of the encapsulation, the sweep deflection of wire bond caused by compound flows obviously results in wire crossover and shorting. Thereby, it is necessary to understand mechanical behaviors of the wire sweep, while it is critical that reduction of the sweep yields clearance of sufficient space between wires. As a rule, a position of a wire with the largest Wire Sweep Index (WSI) possesses the highest possibility of the wire crossover. Recent advances of the encapsulation technologies tend toward smaller scale and higher density, wherein the wire crossover is observed with difficulty. To date, the Computer-Aided Engineering (CAE) technologies have been preferably used in viewing positions of wire crossover. Using the CAE technology, the primary objective of this paper is to develop a useful tool to connect pre-process, filling and structure analyses and post-process, which gives a comprehensive solution for microchip encapsulation. In particular, the wire sweep phenomenon inside the package is found. Furthermore, the CAE users can check the possibility of wire crossover under any processing condition. Thus, application of the CAE technology significantly introducing to mold design for microchip encapsulation is feasible with high reliability.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"1 1","pages":"165-168"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86841497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Nickel solder ball performance for Pb-free LFBGA assembly under oxygenous reflow","authors":"Tien-Tsorng Shih, Wei-Chih Chen, Win-Der Lee, Mu-Chun Wang","doi":"10.1109/IMPACT.2011.6117250","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117250","url":null,"abstract":"Due to the technology improvement of ball-grid-array (BGA) package, the high-pin count concept was derived to the mass production. The low profile fine pitch BGA (LFBGA) package was employed to gain the assembly competition. The smaller diameter of solder ball, 0.3 mm, must be incorporated and the composition of solder ball needs to be modified such as including nickel to strengthen the adhesion capability in IMC layer. Since the oxygen concentration in flow process usually works upon the quality of solder joint such as oxidation causing aged effect and quality of inter-metal compound, the oxygen variance is checked in this study. Furthermore, the flux as solder assistance is also a cardinal factor affecting the solder adherence between LFBGA substrate and solder ball. Adopting the temperature cycling test, shear test and drop test to understand the adhesion ability for lead-free solder balls on LFBGA substrate assisted with several fluxes, the optimal process recipe was obtained. The soldering performance was promoted well.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"10 1","pages":"439-442"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84407575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Estimation for equivalent thermal conductivity of silicon-through vias TSVs used for 3D IC integration","authors":"H. Chien, J. Lau, Y. Chao, R. Tain, M. Dai, W. Lo, M. Kao","doi":"10.1109/IMPACT.2011.6117240","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117240","url":null,"abstract":"In this study, thermal performance of 3D IC integration is investigated. Emphasis is placed on the determination of a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches, TSV thicknesses, passivation thicknesses, and microbump pads. Also, a slice model to imitate a 3D memory stacked chip is adopted to verify the accuracy of the equivalent equations. Finally, the feasibility of these equivalent equations is demonstrated through a simple 3D IC integration structure.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"77 1","pages":"153-156"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83341340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Annealing effect of niobium pentoxide for low voltage electrowetting on dielectric (EWOD)","authors":"Hsiu-Hsiang Chen, C. Fu","doi":"10.1109/IMPACT.2011.6117208","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117208","url":null,"abstract":"In this paper, the high dielectric constants for Nb2O5 (∼25.5) were deposited by a RF reactive magnetron sputtering and respectively annealed at 400 °C O2 ambiance for 30 min in a conventional furnace. Based on the results, an electrowetting optical deflector (EOD) filled with the water (1% sodium dodecyl sulfate (SDS)) and dodecane was fabricated and tested, and the contact angle of the inclined liquid surface on the left and right sidewall can be varied about 70° at 9 V operating voltage. This study provides a practical way to fabricate a high dielectric constant layer for low voltage electrowetting on dielectric (EWOD) application.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"50 1","pages":"401-403"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77549900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Filling TSV of different dimension using galvanic copper deposition","authors":"D. Rohde, C. Jager, Khatera Hazin, A. Uhlig","doi":"10.1109/IMPACT.2011.6117182","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117182","url":null,"abstract":"Filling through silicon via (TSV) with copper is one important process step in 3D-integration. Void free and reliable galvanic copper deposition is essential for yield and lifetime of microelectronic devices. Different TSV applications, as chip stacking and interposer, require different TSV dimensions. This demands high flexibility and applicability for small and large via sizes in the galvanic filling process. This paper compares two different acidic copper systems in respect of their TSV filling properties. Both systems mainly differ in the leveler compound. System A shows super-conformal filling behavior and System B bottom-up filling. The properties of copper being deposited using System A and B respectively vary further in respect of copper grain size homogeneity, stress of the copper deposits, recrystallization temperature and incorporation of additives. The influence of organic copper additives on the mechanical, thermal, and electrical properties of the copper deposits is discussed. Using the example of System B, filling aspects as well as process optimization will be outlined. For process optimization electrochemical potential characteristics (E vs. t) during the filling process are used to identify important filling steps. Filling examples for small as well as large TSV feature sizes will be discussed.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"124 1","pages":"355-358"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88772712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of preformed IMC layer on electromigration of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump","authors":"Y. Orii, K. Toriyama, S. Kohara, H. Noma, K. Okamoto, D. Toyoshima, K. Uenishi","doi":"10.1109/IMPACT.2011.6117170","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117170","url":null,"abstract":"The electromigration (EM) behavior of 80μm pitch C2 (Chip Connection) interconnection [1,2,3] is studied and discussed. C2 is a low cost, peripheral ultra fine pitch flip chip interconnection technology based on the solder capped Cu pillar bumps. The Cu pillar bumps are formed on Al pads that are commonly used in the wirebonding (WB) technique. It thus makes utmost use of the already existing infrastructure. Because C2 bumps are connected to OSP surface treated Cu pads on an organic substrate by reflow with no-clean process, it has a high throughput and is SMT (Surface Mount Technology) compatible. Since the space between dies and substrates is determined by the Cu pillar height, the collapse control of the solder bump is not required. Also, the pre-solder on substrates is also not required. It is an ideal technology for the systems requiring fine pitch structures. Various reliability tests including the thermal cycle tests and thermal humidity bias tests of C2 technology have already been performed. However, only few investigations have been done on the reliability against the EM failures for this technology. In this report, the EM tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and Sn100%. The effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests are studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height is 45μm and the solder height is 25μm. Aged process for pre-formed IMCs was 2,000 hrs at 150°C. The analysis on the samples after the tests showed that the Cu pillar dissociation occurs only in the electron flow direction. However the polarity dependence of IMC layer growths was not detected. C2 test vehicles with pre-formed IMC layers showed no significant electrical resistance increase during the test. Also the consumption of Cu atoms was not observed either from the Cu pillars on the dies or from the Cu pads on the substrates for these test vehicles. The Cu pillar dissociations into the solder were less for the pillars with Ni barrier layers than for those without. The results suggest that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in preventing the Cu atoms from dissociating into the solder. The present study showed a potential ways of forming the Cu pillar joints that are resistant to EM failures.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"3 1","pages":"206-209"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91260580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pressure-dependent variable resistors based on porous polymeric foams with conducting polymer thin films in situ coated on the interior surfaces","authors":"Pen-Cheng Wang, W. Lin, Sz-Yuan Hung, Hsueh-Ju Lu","doi":"10.1109/IMPACT.2011.6117274","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117274","url":null,"abstract":"Pressure-dependent variable resistors were fabricated by coating conducting polymer thin films on the interior surfaces of porous polyurethane (PU) foams with thickness ranging from 1 mm to 5 mm. To coat conducting polymer thin films on the interior surfaces of the porous PU foams, the PU foams were first immersed in 1 M aqueous camphorsulfonic acid (HCSA) solution containing 0.44 M of aniline (monomer solution) and then transferred to another 1 M aqueous camphorsulfonic acid solution containing 0.1 M of ammonium peroxydisulfate (oxidant solution). After the polyaniline (PANI) deposition process by in situ oxidative chemical polymerization of aniline on the interior surfaces of the porous PU foams, the non-conductive PU foams became all-polymer conductive composites. The formation of PANI thin films on the interior surfaces of the porous PU foams was confirmed by optical microscopy and scanning election microscopy (SEM) studies, which showed that no bulk PANI was found to block the porous interstitial space of PU foams after the PANI deposition process. When a PANI-treated conductive PU foam was sandwiched between two pieces of plastic electrodes based on poly(ethyleneterephthalate) (PET) substrates coated with commercially available poly(3,4-ethylenedioxythiophene) doped with poly(styrenesulfonate) (PEDOT:PSS), the whole assembly could act as an all-polymer pressure sensor. By varying the size and thickness of the all-polymer PU-based pressure devices, the responsive ranges can be adjusted for different applications with different applied pressure ranges. With the incorporation of a polymeric cushion as the mechanical buffer layer around the conductive PU composite, the dynamic pressure-responsive range could be further increased. Compared to our previous work, the all-polymer pressure sensors described in the present work showed greater reproducibility when subject to repetitive cycling tests and exhibited greater continuous linear response range.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"12 1","pages":"63-66"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89285247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of underfill material for fine pitch Cu pillar bump","authors":"Huei-Nuan Huang, Yi-Chian Liao, Wen-Tsung Tseng, Chun-Tang Lin, Chi-Hsin Chiu","doi":"10.1109/IMPACT.2011.6117231","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117231","url":null,"abstract":"Underfill (UF) is an important process in flip-chip packaging because of significant impact on the reliability of the IC's package. For three-dimensional integrated circuit (3DIC) demand, fin e pit ch an d fine gap are the market trend in the future due to t he requirements of functionality and performance in electronic device. In this study, a two die stacking, with Cu pillar bumps area of multiple pitches, joint by thermal-compress ion bon ding without flux has been demonstrated in chip on chip fashion. The maximum standoff height after micro bump joint is less than 25 um. Because of different pitch and fine gap structure, underfill dispensing becomes a challenge process for 3DIC stacking. Two different types of underfill were chosen to study in this paper. UF-A has higher viscosity and better stress simulation than UF-B. Different dispensing design were also studied in this paper, and the mechanism of underfill flowing property was determined by scanning acoustic tomograph (SAT) for comparing the effect of dispensing parameter and material.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"60 1","pages":"150-152"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84475220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}