2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)最新文献

{"title":"Annealing effect of niobium pentoxide for low voltage electrowetting on dielectric (EWOD)","authors":"Hsiu-Hsiang Chen, C. Fu","doi":"10.1109/IMPACT.2011.6117208","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117208","url":null,"abstract":"In this paper, the high dielectric constants for Nb2O5 (∼25.5) were deposited by a RF reactive magnetron sputtering and respectively annealed at 400 °C O2 ambiance for 30 min in a conventional furnace. Based on the results, an electrowetting optical deflector (EOD) filled with the water (1% sodium dodecyl sulfate (SDS)) and dodecane was fabricated and tested, and the contact angle of the inclined liquid surface on the left and right sidewall can be varied about 70° at 9 V operating voltage. This study provides a practical way to fabricate a high dielectric constant layer for low voltage electrowetting on dielectric (EWOD) application.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"50 1","pages":"401-403"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77549900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pressure-dependent variable resistors based on porous polymeric foams with conducting polymer thin films in situ coated on the interior surfaces","authors":"Pen-Cheng Wang, W. Lin, Sz-Yuan Hung, Hsueh-Ju Lu","doi":"10.1109/IMPACT.2011.6117274","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117274","url":null,"abstract":"Pressure-dependent variable resistors were fabricated by coating conducting polymer thin films on the interior surfaces of porous polyurethane (PU) foams with thickness ranging from 1 mm to 5 mm. To coat conducting polymer thin films on the interior surfaces of the porous PU foams, the PU foams were first immersed in 1 M aqueous camphorsulfonic acid (HCSA) solution containing 0.44 M of aniline (monomer solution) and then transferred to another 1 M aqueous camphorsulfonic acid solution containing 0.1 M of ammonium peroxydisulfate (oxidant solution). After the polyaniline (PANI) deposition process by in situ oxidative chemical polymerization of aniline on the interior surfaces of the porous PU foams, the non-conductive PU foams became all-polymer conductive composites. The formation of PANI thin films on the interior surfaces of the porous PU foams was confirmed by optical microscopy and scanning election microscopy (SEM) studies, which showed that no bulk PANI was found to block the porous interstitial space of PU foams after the PANI deposition process. When a PANI-treated conductive PU foam was sandwiched between two pieces of plastic electrodes based on poly(ethyleneterephthalate) (PET) substrates coated with commercially available poly(3,4-ethylenedioxythiophene) doped with poly(styrenesulfonate) (PEDOT:PSS), the whole assembly could act as an all-polymer pressure sensor. By varying the size and thickness of the all-polymer PU-based pressure devices, the responsive ranges can be adjusted for different applications with different applied pressure ranges. With the incorporation of a polymeric cushion as the mechanical buffer layer around the conductive PU composite, the dynamic pressure-responsive range could be further increased. Compared to our previous work, the all-polymer pressure sensors described in the present work showed greater reproducibility when subject to repetitive cycling tests and exhibited greater continuous linear response range.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"12 1","pages":"63-66"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89285247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of underfill material for fine pitch Cu pillar bump","authors":"Huei-Nuan Huang, Yi-Chian Liao, Wen-Tsung Tseng, Chun-Tang Lin, Chi-Hsin Chiu","doi":"10.1109/IMPACT.2011.6117231","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117231","url":null,"abstract":"Underfill (UF) is an important process in flip-chip packaging because of significant impact on the reliability of the IC's package. For three-dimensional integrated circuit (3DIC) demand, fin e pit ch an d fine gap are the market trend in the future due to t he requirements of functionality and performance in electronic device. In this study, a two die stacking, with Cu pillar bumps area of multiple pitches, joint by thermal-compress ion bon ding without flux has been demonstrated in chip on chip fashion. The maximum standoff height after micro bump joint is less than 25 um. Because of different pitch and fine gap structure, underfill dispensing becomes a challenge process for 3DIC stacking. Two different types of underfill were chosen to study in this paper. UF-A has higher viscosity and better stress simulation than UF-B. Different dispensing design were also studied in this paper, and the mechanism of underfill flowing property was determined by scanning acoustic tomograph (SAT) for comparing the effect of dispensing parameter and material.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"60 1","pages":"150-152"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84475220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of preformed IMC layer on electromigration of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump","authors":"Y. Orii, K. Toriyama, S. Kohara, H. Noma, K. Okamoto, D. Toyoshima, K. Uenishi","doi":"10.1109/IMPACT.2011.6117170","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117170","url":null,"abstract":"The electromigration (EM) behavior of 80μm pitch C2 (Chip Connection) interconnection [1,2,3] is studied and discussed. C2 is a low cost, peripheral ultra fine pitch flip chip interconnection technology based on the solder capped Cu pillar bumps. The Cu pillar bumps are formed on Al pads that are commonly used in the wirebonding (WB) technique. It thus makes utmost use of the already existing infrastructure. Because C2 bumps are connected to OSP surface treated Cu pads on an organic substrate by reflow with no-clean process, it has a high throughput and is SMT (Surface Mount Technology) compatible. Since the space between dies and substrates is determined by the Cu pillar height, the collapse control of the solder bump is not required. Also, the pre-solder on substrates is also not required. It is an ideal technology for the systems requiring fine pitch structures. Various reliability tests including the thermal cycle tests and thermal humidity bias tests of C2 technology have already been performed. However, only few investigations have been done on the reliability against the EM failures for this technology. In this report, the EM tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and Sn100%. The effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests are studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height is 45μm and the solder height is 25μm. Aged process for pre-formed IMCs was 2,000 hrs at 150°C. The analysis on the samples after the tests showed that the Cu pillar dissociation occurs only in the electron flow direction. However the polarity dependence of IMC layer growths was not detected. C2 test vehicles with pre-formed IMC layers showed no significant electrical resistance increase during the test. Also the consumption of Cu atoms was not observed either from the Cu pillars on the dies or from the Cu pads on the substrates for these test vehicles. The Cu pillar dissociations into the solder were less for the pillars with Ni barrier layers than for those without. The results suggest that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in preventing the Cu atoms from dissociating into the solder. The present study showed a potential ways of forming the Cu pillar joints that are resistant to EM failures.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"3 1","pages":"206-209"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91260580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Filling TSV of different dimension using galvanic copper deposition","authors":"D. Rohde, C. Jager, Khatera Hazin, A. Uhlig","doi":"10.1109/IMPACT.2011.6117182","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117182","url":null,"abstract":"Filling through silicon via (TSV) with copper is one important process step in 3D-integration. Void free and reliable galvanic copper deposition is essential for yield and lifetime of microelectronic devices. Different TSV applications, as chip stacking and interposer, require different TSV dimensions. This demands high flexibility and applicability for small and large via sizes in the galvanic filling process. This paper compares two different acidic copper systems in respect of their TSV filling properties. Both systems mainly differ in the leveler compound. System A shows super-conformal filling behavior and System B bottom-up filling. The properties of copper being deposited using System A and B respectively vary further in respect of copper grain size homogeneity, stress of the copper deposits, recrystallization temperature and incorporation of additives. The influence of organic copper additives on the mechanical, thermal, and electrical properties of the copper deposits is discussed. Using the example of System B, filling aspects as well as process optimization will be outlined. For process optimization electrochemical potential characteristics (E vs. t) during the filling process are used to identify important filling steps. Filling examples for small as well as large TSV feature sizes will be discussed.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"124 1","pages":"355-358"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88772712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Palladium surface finishes for copper wire bonding (Part I: The selection of surface finishes)","authors":"M. Ozkok, Bill Kao, H. Clauberg","doi":"10.1109/IMPACT.2011.6117179","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117179","url":null,"abstract":"During the past two years, fine pitch copper wire bonding has finally entered high volume production. It is estimated that nearly 15% of all wire bonders used in production are now equipped for copper wire bonding. Most of these are used exclusively for copper wire bonding. In terms of pitch, copper wire is only barely lagging behind the most advanced gold applications. The most commonly used copper wire is 20um in diameter and 18um copper wire is entering final qualification. Evaluations with even finer wire are underway. Although some technical challenges remain, many years of research have now resolved most of the problems associated with copper wire bonding and attention is beginning to shift from merely ensuring reliable manufacturing processes to optimizing processes for efficiency and throughput. The most advanced wire bonders now have pre-configured processes specifically designed for copper. In addition to throughput optimization, further cost reductions are being sought. Among these is the desire to eliminate the high-cost gold not just from the wire, but also from the substrate. On the substrate side the electronics packaging industry still works with electrolytic nickel / electrolytic (soft) gold (Ni/Au) for copper wire bond applications. This surface finish works with copper wire bonding but includes some disadvantages, such as: — Thick expensive Au layers of 0.1 to 0.4μm — Electrically connected pads (bussing for the plating) which require added space on the substrate. — Pd-coated copper wire often delivers better results on gold covered finishes, but is two to three times more expensive as pure copper wire. Furthermore electrolytic Ni/Au was not chosen as a result of in-depth investigations for the most effective surface finish. The selection was made because it was the surface finish with the highest distribution in the market for wire bond packages. This paper is offering the results of a two company joint work regarding an alternative copper wire bondable surface finish for substrates mainly with palladium as the final copper wire bondable layer. This offers further cost reduction possibilities. Furthermore, copper palladium intermetallics are regarded as very reliable.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"1 1","pages":"37-41"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89629057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High power electronics package: From modeling to implementation","authors":"C. Yuan, R. Kregting, H. Ye, W. V. van Driel, S. Gielen, G. Zhang","doi":"10.1109/IMPACT.2011.6117183","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117183","url":null,"abstract":"Power electronics, such as high power RF components and high power LEDs, requires the combination of robust and reliable package structures, materials, and processes to guarantee their functional performance and lifetime. We started with the thermal and thermal-mechanical modeling of such component performances. With robust validation. Afterwards, an online testing method, design rules, and new structures/modifications have been implemented to improve the performance and reliability of high power electronics. This paper reviews our efforts on the RF transistors and high power LED's developments.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"446 1","pages":"249-252"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78192675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigations of adhesion between Cu and Benzocyclobutene (BCB) polymer dielectric for 3D integration applications","authors":"W. C. Huang, C. Ko, S. Hu, J. Leu, K. N. Chen","doi":"10.1109/IMPACT.2011.6117239","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117239","url":null,"abstract":"In this paper, the adhesion strength between Cu metal and Benzocyclobutene (BCB) polymer dielectric was investigated and reported. The relation between the adhesion strength and thickness of metal layer and the relation between the adhesion strength and stacking order of copper and BCB polymer layer are discussed as well. Finally, the concept of an extra layer between Cu metal and BCB polymer layer to improve the adhesion strength was evaluated. The results of this research can provide important guidelines of hybrid bonding and underfill for 3D integration applications.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"56 1","pages":"363-365"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83947748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A fully integrated circuit for MEMS vibrating gyroscope using standard 0.25um CMOS process","authors":"Sheng-Ren Chiu, Chung-Yang Sue, Lu-Pu Liao, Li-Tao Teng, Y. Hsu, Y. Su","doi":"10.1109/IMPACT.2011.6117258","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117258","url":null,"abstract":"This paper presents an all-in-one fully integrated circuit solution for a vibrating micro-electromechanical gyroscope system using standard 0.25um 1P5M low voltage CMOS process. The analog parts of the system include a trans-impedance amplifier (TIA) with adaptive gain control (AGC) for the resonator driving loop, a sigma-delta modulator with gain/offset trimming function for the Coriolis signal read-out and a modified all PMOS charge pump for the high DC voltage. The digital signal processing parts include a trimming/control logic circuit and an I2C interface. SOG-bulk micromachining and deep reactive ion etching (DRIE) are adopted to fabricate the gyroscope sensor element with high aspect-ratio sensing structure and high yield. The experimental results indicate that the noise floor achieves 0.051° / s/ √Hz and the scale factor is 7mV/ °/s of the proposed two chip MEMS gyroscope system.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"50 1","pages":"315-318"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91137848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-speed electrical design study for 3D-IC packaging technology","authors":"R. Sung, K. Chiang, D. Lee, M. Ma","doi":"10.1109/IMPACT.2011.6117223","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117223","url":null,"abstract":"As the advance of the packaging technology for the electrical consuming demands, it requires for more functions or increasing the density of devices within a smaller space. By the capabilities of the 3D-IC technology, it could support a design included smaller size, high-speed and multi-functions. One of the 3D-IC techs, the stacking with Through-Silicon-Via (TSV), plays a very important role. It shortens the path, and hence, increases the bandwidth of the device. In this study, we evaluate the TSV effects in usual high-speed electrical designs. There are two issues, the impedance-control and isolation. By using the EM simulation solver, we estimate the performances of different designed models about these two issues. And, this result should have the benefits for the development on the designs in the interposer substrates used for 3D-IC technology.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"59 1","pages":"144-146"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80835594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}