预成形IMC层对外围超细间距C2倒装芯片电迁移的影响

Y. Orii, K. Toriyama, S. Kohara, H. Noma, K. Okamoto, D. Toyoshima, K. Uenishi
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引用次数: 4

摘要

研究并讨论了80μm间距C2 (Chip Connection)互连的电迁移(EM)行为[1,2,3]。C2是一种低成本的外设超细间距倒装芯片互连技术,基于焊料覆盖的铜柱凸点。铜柱凸起是在铝焊盘上形成的,铝焊盘通常用于线连接(WB)技术。因此,它最大限度地利用了现有的基础设施。由于C2凸起通过无清洁工艺回流连接到有机基板上的OSP表面处理铜垫,因此具有高吞吐量,并且与SMT(表面贴装技术)兼容。由于模具和基板之间的空间是由铜柱高度决定的,所以不需要焊料凸点的坍塌控制。此外,基板上的预焊料也不需要。对于需要细间距结构的系统,它是一种理想的技术。已经进行了C2技术的热循环试验和热湿偏置试验等各种可靠性试验。然而,对该技术抗电磁故障可靠性的研究很少。在本报告中,对80μm间距的C2倒装芯片互连进行了EM测试。用两种不同的焊料材料Sn/2.5Ag和Sn100%进行互连测试。研究了镍阻挡层对铜柱和预形成金属间化合物(IMC)层的影响。试验车辆的电磁测试条件为7-10 kA/cm2,温度为125-170℃。铜柱高度为45μm,焊料高度为25μm。预成形IMCs的时效过程为在150℃下时效2000小时。实验后对样品的分析表明,铜柱解离只发生在电子流方向。然而,没有检测到IMC层生长的极性依赖性。带有预成型IMC层的C2测试车辆在测试过程中电阻没有明显增加。此外,无论是从模具上的铜柱还是从这些测试车辆的衬底上的铜垫上,都没有观察到Cu原子的消耗。有Ni阻挡层的铜柱与钎料的解离比没有Ni阻挡层的铜柱少。结果表明,预先形成的IMC层的形成和Ni势垒层的插入可以有效地防止Cu原子解离到焊料中。目前的研究显示了一种形成抗电磁破坏的铜柱接头的潜在方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Effect of preformed IMC layer on electromigration of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump
The electromigration (EM) behavior of 80μm pitch C2 (Chip Connection) interconnection [1,2,3] is studied and discussed. C2 is a low cost, peripheral ultra fine pitch flip chip interconnection technology based on the solder capped Cu pillar bumps. The Cu pillar bumps are formed on Al pads that are commonly used in the wirebonding (WB) technique. It thus makes utmost use of the already existing infrastructure. Because C2 bumps are connected to OSP surface treated Cu pads on an organic substrate by reflow with no-clean process, it has a high throughput and is SMT (Surface Mount Technology) compatible. Since the space between dies and substrates is determined by the Cu pillar height, the collapse control of the solder bump is not required. Also, the pre-solder on substrates is also not required. It is an ideal technology for the systems requiring fine pitch structures. Various reliability tests including the thermal cycle tests and thermal humidity bias tests of C2 technology have already been performed. However, only few investigations have been done on the reliability against the EM failures for this technology. In this report, the EM tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and Sn100%. The effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests are studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height is 45μm and the solder height is 25μm. Aged process for pre-formed IMCs was 2,000 hrs at 150°C. The analysis on the samples after the tests showed that the Cu pillar dissociation occurs only in the electron flow direction. However the polarity dependence of IMC layer growths was not detected. C2 test vehicles with pre-formed IMC layers showed no significant electrical resistance increase during the test. Also the consumption of Cu atoms was not observed either from the Cu pillars on the dies or from the Cu pads on the substrates for these test vehicles. The Cu pillar dissociations into the solder were less for the pillars with Ni barrier layers than for those without. The results suggest that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in preventing the Cu atoms from dissociating into the solder. The present study showed a potential ways of forming the Cu pillar joints that are resistant to EM failures.
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