IEEE Computer Architecture Letters最新文献_第6页

UniCNet: Unified Cycle-Accurate Simulation for Composable Chiplet Network With Modular Design-Integration Workflow 基于模块化设计集成工作流的可组合芯片网络的统一周期精确仿真

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-13 DOI: 10.1109/LCA.2026.3653809

Peilin Wang;Mingyu Wang;Zhirong Ye;Tao Lu;Zhiyi Yu

引用次数: 0

Xami: Expert-Aware Adaptive Compression for Mixture-of-Experts on Sparse Tensor Cores 稀疏张量核上混合专家的专家感知自适应压缩

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-31 DOI: 10.1109/LCA.2026.3679449

Johnson Umeike;Bahar Asgari

{"title":"Xami: Expert-Aware Adaptive Compression for Mixture-of-Experts on Sparse Tensor Cores","authors":"Johnson Umeike;Bahar Asgari","doi":"10.1109/LCA.2026.3679449","DOIUrl":"https://doi.org/10.1109/LCA.2026.3679449","url":null,"abstract":"Mixture-of-Experts (MoE) models reduce active computation through sparse routing; yet their significant memory overhead due to retaining the full parameter footprint of all experts remains a deployment challenge. To address this, we present <monospace><italic>Xami</i><monospace>, an expert-aware adaptive compression framework that exploits routing heterogeneity to apply differentiated structured sparsity across experts. By profiling per-layer activation distributions, <monospace><italic>Xami</i><monospace> preserves frequently activated experts at higher fidelity while more aggressively compressing infrequent ones, all while remaining compatible with native 2:4 Sparse Tensor Core (<monospace><italic>SpTCs</i><monospace>) hardware execution. Across different MoE architectures, <monospace><italic>Xami</i><monospace> consistently improves model-level compression over uniform 2:4 sparsity with minimal accuracy loss and competitive inference throughput. Our results demonstrate that expert heterogeneity can be translated into practical memory savings, achieving up to 2.4× compression over dense compared to just 1.8× achieved by uniform 2:4, without modifying the underlying hardware execution model, providing a highly desirable path toward more efficient MoE inference.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"154-157"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FastTrackGPU: Static-Analysis–Guided Analytical Modeling for Softcore GPUs FastTrackGPU：软核gpu的静态分析导向分析建模

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-25 DOI: 10.1109/LCA.2026.3677349

Chihyo Ahn;Shinnung Jeong;Liam Paul Cooper;Ruobing Han;Huanzhi Pu;Nicholas Parnenzini;Jisheng Zhao;Blaise Tine;Hyesoon Kim

引用次数: 0

Calibrating DRAMPower Model for HPC: A Runtime Perspective From Real-Time Measurements 校准高性能计算的DRAMPower模型：从实时测量的运行时角度

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2025-09-29 DOI: 10.1109/LCA.2025.3615711

Xinyu Shi;Dina Abdelbaky;Thomas Ilsche;Saeideh Alinezhad Chamazcoti;Timon Evenblij;Mohit Gupta;Francky Catthoor

{"title":"Calibrating DRAMPower Model for HPC: A Runtime Perspective From Real-Time Measurements","authors":"Xinyu Shi;Dina Abdelbaky;Thomas Ilsche;Saeideh Alinezhad Chamazcoti;Timon Evenblij;Mohit Gupta;Francky Catthoor","doi":"10.1109/LCA.2025.3615711","DOIUrl":"https://doi.org/10.1109/LCA.2025.3615711","url":null,"abstract":"Main memory’s rising energy consumption has emerged as a critical challenge in modern computing architectures, particularly in large-scale systems, driven by frequent access patterns, growing data volumes, and insufficient power management strategies. Accurate modeling of DRAM power consumption is essential to address this challenge and optimize energy efficiency. However, existing modeling tools often rely on vendor-provided datasheet values that are obtained under worst-case or idealized conditions. As a result, they fail to capture important system-level factors such as temperature variations, chip aging, and workload-induced variability, which leads to significant discrepancies between estimated and actual power consumption observed in real deployments. In this work, we propose a runtime calibration methodology for the DRAMPower model using energy measurements collected from real-system experiments. By applying custom memory benchmarks on an HPC cluster and leveraging fine-grained power monitoring infrastructure, we refine key current parameters (IDD values) in the model. Our calibration reduces the average energy estimation error to less than 5%, substantially improving modeling accuracy and making DRAMPower a more reliable tool for power-aware system design and optimization on the target server platform.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"218-221"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

KiF: Accelerating Low-Batch LLM Inference Using In-Flash KV Cache KiF：使用flash内KV缓存加速低批量LLM推理

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-04 DOI: 10.1109/LCA.2026.3689575

Haeeun Jung;Jaeyong Lee;Sanggu Lee;Huiwon Yun;Dongsuk Jeon;Nam Sung Kim;Jihong Kim

引用次数: 0

Rules, Not Rankings: Interpretable AI for Processor Microarchitecture Design Analysis 规则，而不是排名：处理器微架构设计分析的可解释AI

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-13 DOI: 10.1109/LCA.2026.3692901

Abdoulaye Gamatié;Lincen Yang;Paulo Pimenta

引用次数: 0

BISC: Rethinking Instruction Set Abstractions at Block Granularity BISC：在块粒度上重新思考指令集抽象

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-21 DOI: 10.1109/LCA.2026.3690895

An Zhong;Hanzhi Hu;Zirui Ma;Mengzhu Li;Haibin Wu;Fulin Zhang;Jinyi Deng;Ceyu Xu;Wenming Li;Yang Hu;Jian Weng

{"title":"BISC: Rethinking Instruction Set Abstractions at Block Granularity","authors":"An Zhong;Hanzhi Hu;Zirui Ma;Mengzhu Li;Haibin Wu;Fulin Zhang;Jinyi Deng;Ceyu Xu;Wenming Li;Yang Hu;Jian Weng","doi":"10.1109/LCA.2026.3690895","DOIUrl":"https://doi.org/10.1109/LCA.2026.3690895","url":null,"abstract":"Most widely deployed ISAs for general-purpose processors expose a centralized register file and instruction-granular control flow, forcing modern CPUs to rely on complex microarchitectural mechanisms to reconcile execution with architectural state. Even in simple in-order designs, these abstractions impose back-and-forth execution overheads, while more aggressive processors further amplify them through register renaming, speculation, and in-order retirement. This letter presents the Block-based Instruction Set Computer (BISC), which rethinks ISA abstractions at block granularity. BISC eliminates architectural destination registers by binding each instruction's result to its position within a block, enabling block-local execution driven by operand availability while preserving control-flow semantics across blocks. Control flow is resolved at block entry, amortizing fetch and control overhead across multiple operations and enabling efficient expression of conditional selection without additional control-flow edges. We evaluate BISC using a single-issue in-order core with comparable area to a RISC-V baseline. Despite executing more operations and incurring a larger code footprint, BISC achieves a 34% geometric mean speedup across benchmarks. These results demonstrate that ISA-level execution abstractions play a critical role in processor efficiency, independent of microarchitectural optimizations.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"222-225"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware-Accelerated Parallel Wrong-Path Execution for Spectre Gadget Detection 用于幽灵小工具检测的硬件加速并行错误路径执行

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-06-04 DOI: 10.1109/LCA.2026.3700174

Fangzheng Lin;Zeyu Gao;Yanru Lin;Yangyu Chen;Hiroshi Sasaki

引用次数: 0

Fast Inter-Enclave Communication Encryption 快速飞地间通信加密

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-06 DOI: 10.1109/LCA.2026.3671373

Pouria Peykani Sani;Ali Mohammadpur-Fard;Shamiek Mangipudi;Sina Darabi;Francesco Regazzoni;Patrick Eugster

{"title":"Fast Inter-Enclave Communication Encryption","authors":"Pouria Peykani Sani;Ali Mohammadpur-Fard;Shamiek Mangipudi;Sina Darabi;Francesco Regazzoni;Patrick Eugster","doi":"10.1109/LCA.2026.3671373","DOIUrl":"https://doi.org/10.1109/LCA.2026.3671373","url":null,"abstract":"Trusted execution environments (TEEs) provide applications – notably executing in third-party infrastructures like the cloud – with an encrypted and isolated execution space, decoupling programs and their data from other resident applications and privileged software (e.g., operating system and hypervisor). This confinement of trust to hardware significantly reduces the attack surface. However, distributed cloud applications deployed in TEEs often require frequent communication across worker nodes within a cluster. Ensuring the confidentiality, authenticity, and integrity of inter-TEE data exchanges necessitates secure communication channels, typically enforced through encryption that introduces I/O throughput bottlenecks. In this paper, we demonstrate that software-based encryption—relying solely on central processing unit (CPU) computation—fails to keep pace with the high-throughput interconnects between TEEs while consuming substantial CPU resources. To address this inefficiency, we propose a parallelized channel encryption hardware within the existing memory encryption engine (MEE). Initial experiments show that our approach has the potential to reduce communication channel encryption overhead to just a few CPU cycles resulting in orders of magnitude speedup over conventional software-based approaches.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"89-92"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148478821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploration of Algorithm-Hardware Co-Design for Floating-Point Digital Compute-in-Memory 浮点数字内存计算算法-硬件协同设计的探索

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-19 DOI: 10.1109/LCA.2026.3675952

Xiaochen Peng;Haruki Mori;Abhiroop Bhattacharjee;Brian Crafton;Hidehiro Fujiwara;Kerem Akarvardar

{"title":"Exploration of Algorithm-Hardware Co-Design for Floating-Point Digital Compute-in-Memory","authors":"Xiaochen Peng;Haruki Mori;Abhiroop Bhattacharjee;Brian Crafton;Hidehiro Fujiwara;Kerem Akarvardar","doi":"10.1109/LCA.2026.3675952","DOIUrl":"https://doi.org/10.1109/LCA.2026.3675952","url":null,"abstract":"Digital compute-in-memory (DCIM) has emerged as a promising technique to accelerate deep neural networks by minimizing data-movement and performing near/in-memory computation. While floating-point (FP) arithmetic being widely used in modern AI workloads due to its numerical robustness, supporting FP-DCIM brings design challenges, including dynamic range management, accumulation precision, FP arithmetic strategies and overheads. To address these challenges, we developed hardware-accurate convolutional and fully-connected layer operators to precisely emulate the multiply-and-add (MAC) operation of FP-DCIM. This enabled end-to-end accuracy evaluation under specific hardware design choices along with their quantified impact on both numerical behavior and hardware efficiency. We conduct a comprehensive algorithm-hardware co-design exploration across diverse AI workloads to identify the optimal FP-DCIM architecture that minimizes hardware cost under strict accuracy constraints. Specifically, we show that product mantissa can be truncated to 14b and 12b for FP16-DCIM and FP8-DCIM respectively with no accuracy degradation, while incorporating rounding allows even lower bit-width. These observations further enable exponent-dependent MAC-skipping as an orthogonal iso-accurate strategy for additional energy savings. Hardware evaluation on 3nm FP16-DCIM macros indicates that combining the above strategies can reduce power by >37% without compromising accuracy performance.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"118-121"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147665399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0