LTE: Lightweight and Time-Efficient Hardware Encoder for Post-Quantum Scheme HQC

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2024-07-30 DOI:10.1109/LCA.2024.3435495

Yazheng Tu;Pengzhou He;Chip-Hong Chang;Jiafeng Xie

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Abstract

Post-quantum cryptography (PQC) has gained increasing attention across the hardware research community, especially after the National Institute of Standards and Technology (NIST) started the PQC standardization process. There are, however, very few hardware implementations reported for the Hamming Quasi-Cyclic (HQC), which is one of the NIST fourth-round PQC candidates. As encoding is an important step in code-based public key encryption scheme, this paper presents a L ightweight and T ime- E fficient (LTE) hardware encoder for HQC. Our proposed design features a streamlined data flow setup to manage the iterative computations between the Reed-Solomon encoder and the Reed-Muller encoder, and a detailed analysis to obtain an optimized Galois field multiplier. The proposed LTE encoder is also implemented on an FPGA platform to demonstrate its area-time efficiency. Our evaluation shows that the proposed hardware implementation of HQC encoder outperforms the most recently reported state-of-the-art hardware implementation with 34.5%, 26.7%, and 35.2% reduction in area-delay product (ADP) for hqc-128, hqc-192, and hqc-256, respectively.

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LTE：用于后量子方案 HQC 的轻量级省时硬件编码器

后量子密码学（PQC）越来越受到硬件研究界的关注，尤其是在美国国家标准与技术研究院（NIST）启动 PQC 标准化进程之后。然而，作为 NIST 第四轮 PQC 候选方案之一的 Hamming Quasi-Cyclic (HQC) 的硬件实现却鲜有报道。由于编码是基于代码的公开密钥加密方案的重要步骤，本文提出了一种轻量级、省时（LTE）的 HQC 硬件编码器。我们提出的设计采用精简的数据流设置来管理里德-所罗门编码器和里德-穆勒编码器之间的迭代计算，并通过详细分析获得优化的伽罗瓦场乘法器。我们还在 FPGA 平台上实现了拟议的 LTE 编码器，以展示其面积-时间效率。我们的评估结果表明，所提出的 HQC 编码器硬件实现优于最新报道的最先进硬件实现，在 hqc-128、hqc-192 和 hqc-256 的面积-延迟积 (ADP) 方面分别减少了 34.5%、26.7% 和 35.2%。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.