IEEE Computer Architecture Letters最新文献

Editorial: A Letter From the Editor-in-Chief of IEEE Computer Architecture Letters

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2025-01-28 DOI: 10.1109/LCA.2025.3528276

Sudhanva Gurumurthi;Mattan Erez

引用次数: 0

2024 Reviewers List 2024审稿人名单

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2025-01-22 DOI: 10.1109/LCA.2025.3528619

引用次数: 0

SPAM: Streamlined Prefetcher-Aware Multi-Threaded Cache Covert-Channel Attack

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2025-01-14 DOI: 10.1109/LCA.2025.3529213

E. Kritheesh;Biswabandan Panda

{"title":"SPAM: Streamlined Prefetcher-Aware Multi-Threaded Cache Covert-Channel Attack","authors":"E. Kritheesh;Biswabandan Panda","doi":"10.1109/LCA.2025.3529213","DOIUrl":"https://doi.org/10.1109/LCA.2025.3529213","url":null,"abstract":"Last-level cache (LLC) covert-channels exploit the cache timing differences to transmit information. In recent works, the attacks rely on a single sender and a single receiver. Streamline is the state-of-the-art cache covert channel attack that uses a shared array of addresses mapped to the payload bits, allowing parallelization of the encoding and decoding of bits. As multi-core systems are ubiquitous, multiple senders and receivers can be used to create a high bandwidth cache covert channel. However, this is not the case, and the bandwidth per thread is limited by various factors. We extend Streamline to a multi-threaded Streamline, where the senders buffer a few thousand bits at the LLC for the receivers to decode. We observe that these buffered bits are prone to eviction by the co-running processes before they are decoded. We propose SPAM, a multi-threaded covert-channel at the LLC. SPAM shows that fewer but faster senders must encode for more receivers to reduce this time frame. This ensures resilience to noise coming from cache activities of co-running applications. SPAM uses two different access patterns for the sender(s) and the receiver(s). The sender access pattern of the addresses is modified to leverage the hardware prefetchers to accelerate the loads while encoding. The receiver access pattern circumvents the hardware prefetchers for accurate load latency measurements. We demonstrate SPAM on a six-core (12-threaded) system, achieving a bit-rate of 12.21 MB/s at an error rate of 9.02% which is an improvement of over 70% over the state-of-the-art multi-threaded Streamline for comparable error rates when 50% of the co-running threads stress the cache system.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"24 1","pages":"25-28"},"PeriodicalIF":1.4,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cooperative Memory Deduplication With Intel Data Streaming Accelerator

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2025-01-09 DOI: 10.1109/LCA.2025.3527458

Houxiang Ji;Minho Kim;Seonmu Oh;Daehoon Kim;Nam Sung Kim

引用次数: 0

High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network 基于Winograd的高性能卷积神经网络加速器架构

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2025-01-08 DOI: 10.1109/LCA.2025.3525970

Vardhana M;Rohan Pinto

引用次数: 0

PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors PINSim：用于模拟智能视觉传感器的处理内传感器和近传感器模拟器

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2024-12-25 DOI: 10.1109/LCA.2024.3522777

Sepehr Tabrizchi;Mehrdad Morsali;David Pan;Shaahin Angizi;Arman Roohi

{"title":"PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors","authors":"Sepehr Tabrizchi;Mehrdad Morsali;David Pan;Shaahin Angizi;Arman Roohi","doi":"10.1109/LCA.2024.3522777","DOIUrl":"https://doi.org/10.1109/LCA.2024.3522777","url":null,"abstract":"This letter introduces PINSim, a user-friendly and flexible framework for simulating emerging smart vision sensors in the early design stages. PINSim enables the realization of integrated sensing and processing near and in the sensor, effectively addressing challenges such as data movement and power-hungry analog-to-digital converters. The framework offers a flexible interface and a wide range of design options for customizing the efficiency and accuracy of processing-near/in-sensor-based accelerators using a hierarchical structure. Its organization spans from the device level upward to the algorithm level. PINSim realizes instruction-accurate evaluation of circuit-level performance metrics. PINSim achieves over <inline-formula><tex-math>$25,000times$</tex-math></inline-formula> speed-up compared to SPICE simulation with less than a 4.1% error rate on average. Furthermore, it supports both multilayer perceptron (MLP) and convolutional neural network (CNN) models, with limitations determined by IoT budget constraints. By facilitating the exploration and optimization of various design parameters, PiNSim empowers researchers and engineers to develop energy-efficient and high-performance smart vision sensors for a wide range of applications.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"24 1","pages":"17-20"},"PeriodicalIF":1.4,"publicationDate":"2024-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ZoneBuffer: An Efficient Buffer Management Scheme for ZNS SSDs ZoneBuffer：适用于 ZNS 固态硬盘的高效缓冲区管理方案

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2024-12-16 DOI: 10.1109/LCA.2024.3498103

Hongtao Wang;Peiquan Jin

{"title":"ZoneBuffer: An Efficient Buffer Management Scheme for ZNS SSDs","authors":"Hongtao Wang;Peiquan Jin","doi":"10.1109/LCA.2024.3498103","DOIUrl":"https://doi.org/10.1109/LCA.2024.3498103","url":null,"abstract":"The introduction of Zoned Namespace SSDs (ZNS SSDs) presents new challenges for existing buffer management schemes. In addition to traditional SSD characteristics such as read/write asymmetry and limited write endurance, ZNS SSDs possess unique constraints, such as requiring sequential writes within each zone. These features make conventional buffering policies incompatible with ZNS SSDs. This paper introduces ZoneBuffer, a novel buffering scheme designed specifically for ZNS SSDs. ZoneBuffer's innovation lies in two key aspects. First, it introduces a new buffer structure comprising a Work Region and a Priority Region. The Priority Region is further divided into a clean page queue and a zone cluster of dirty pages. By confining buffer replacement to the Priority Region, ZoneBuffer ensures optimization for ZNS SSDs. Second, ZoneBuffer incorporates a lifetime-based clustering algorithm to group dirty pages within the Priority Region, optimizing write operations. Preliminary experiments conducted on a real ZNS SSD demonstrate the effectiveness of ZoneBuffer. Compared with conventional schemes like LRU and CFLRU, the results indicate that ZoneBuffer significantly improves performance.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"23 2","pages":"239-242"},"PeriodicalIF":1.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Straw: A Stress-Aware WL-Based Read Reclaim Technique for High-Density NAND Flash-Based SSDs Straw：一种应力感知的基于wl的高密度NAND闪存固态硬盘读回收技术

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2024-12-12 DOI: 10.1109/LCA.2024.3516205

Myoungjun Chun;Jaeyong Lee;Inhyuk Choi;Jisung Park;Myungsuk Kim;Jihong Kim

引用次数: 0

Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices 消除位图压缩矩阵的无效计算

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2024-12-12 DOI: 10.1109/LCA.2024.3516057

Chaithanya Krishna Vadlamudi;Bahar Asgari

引用次数: 0

IntervalSim++: Enhanced Interval Simulation for Unbalanced Processor Designs IntervalSim++：非平衡处理器设计的增强间隔仿真