Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2025-07-10 DOI:10.1109/LCA.2025.3587293

Jumin Kim;Seungmin Baek;Minbok Wi;Hwayong Nam;Michael Jaemin Kim;Sukhan Lee;Kyomin Sohn;Jung Ho Ahn

引用次数: 0

Abstract

Per-Row Activation Counting (PRAC), a DRAM read disturbance mitigation method, modifies key DRAM timing parameters, reportedly causing significant performance overheads in simulator-based studies. However, given known discrepancies between simulators and real hardware, real-machine experiments are vital for accurate PRAC performance estimation. We present the first real-machine performance analysis of PRAC. After verifying timing modifications on the latest CPUs using microbenchmarks, our analysis shows that PRAC’s average and maximum overheads are just 1.06% and 3.28% for the SPEC CPU2017 workloads—up to 9.15× lower than simulator-based reports. Further, we show that the close page policy minimizes this overhead by effectively hiding the elongated DRAM row precharge operations due to PRAC from the critical path.

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真实硬件上的每行激活计数：揭开性能开销的神秘面纱

逐行激活计数（PRAC）是一种缓解DRAM读取干扰的方法，它修改了关键的DRAM时序参数，据报道，在基于模拟器的研究中，这会导致显著的性能开销。然而，鉴于模拟器和真实硬件之间的已知差异，真实机实验对于准确估计PRAC性能至关重要。我们首次对PRAC进行了实机性能分析。在使用微基准测试验证最新cpu上的时序修改后，我们的分析表明，在SPEC CPU2017工作负载下，PRAC的平均开销和最大开销仅为1.06%和3.28%，比基于模拟器的报告低9.15倍。此外，我们还表明，关闭页策略通过有效地隐藏由于关键路径上的PRAC而延长的DRAM行预充值操作，从而最大限度地减少了这种开销。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.