IEEE Computer Architecture Letters最新文献_第2页

Precision-Flexible Processing Units for Fully Utilizing Internal Bandwidth in PIM 充分利用PIM内部带宽的精密柔性处理单元

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-09-28 DOI: 10.1109/LCA.2026.3737969

Suhwan Kim;Changyong Eom;Sieun Moon;Siu Jeong;Yelim Han;Jaehyuk Huh

引用次数: 0

NeuroMTA: Programmable Simulation Framework for Multi-Tile NPU Architectures NeuroMTA：多块NPU架构的可编程仿真框架

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-07-22 DOI: 10.1109/LCA.2026.3716090

Seongwook Kim;Seokin Hong

引用次数: 0

On the Feasibility Boundaries of LLM Prefill Inference on Unified-Memory Edge SoCs 统一存储边缘soc上LLM预填充推理的可行性边界

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-06-15 DOI: 10.1109/LCA.2026.3703423

Juyeon Lee;Jiayue Wang;Soojung Ryu;Hyuk-Jae Lee

引用次数: 0

Packet-Level CXL.cache Analysis With ${sf OpenCIS}$OpenCIS 使用${sf OpenCIS}$OpenCIS进行包级cxl .缓存分析

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-08-27 DOI: 10.1109/LCA.2026.3728300

Xiangqun Zhang;Juhyung Park;Seonggyun Oh;Kyeyoon Park;Jinki Han;Eunji Lee;Sungjin Lee;Yeseong Kim;Bryan S. Kim

{"title":"Packet-Level CXL.cache Analysis With ${sf OpenCIS}$OpenCIS","authors":"Xiangqun Zhang;Juhyung Park;Seonggyun Oh;Kyeyoon Park;Jinki Han;Eunji Lee;Sungjin Lee;Yeseong Kim;Bryan S. Kim","doi":"10.1109/LCA.2026.3728300","DOIUrl":"https://doi.org/10.1109/LCA.2026.3728300","url":null,"abstract":"CXL.cache enables devices to coherently access host memory, but its behavior is difficult to understand without packet-level visibility into ownership transfers, cache line invalidations, and host-device request flows. Packet-level visibility into CXL.cache is thus crucial for CXL research, but it is largely ignored by existing CXL tools. Therefore, we present <inline-formula><tex-math>${sf OpenCIS}$</tex-math></inline-formula>, an open-source CXL simulation platform on the transaction layer that supports CXL.cache and flexible CXL topologies. We show that <inline-formula><tex-math>${sf OpenCIS}$</tex-math></inline-formula>’s transaction-layer visibility is useful for both CXL.cache workload-side optimization and protocol-side exploration by implementing two workloads using <inline-formula><tex-math>${sf OpenCIS}$</tex-math></inline-formula>, namely PageRank and FlushData. For PageRank, we explore the importance of CXL-aware workload-side optimization by showing the differences between two workload-sharding approaches under a multi-accelerator scenario. For FlushData, we reveal the benefits of a new CXL.cache opcode that actively pushes needed data to accelerators from the host.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 2","pages":"351-354"},"PeriodicalIF":2.0,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11668657","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149033444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Back-Invalidate Timing: Coherence Channels in CXL 3.x Device-Coherent Memory 反向无效时序：CXL 3中的相干通道。x Device-Coherent Memory

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-09-29 DOI: 10.1109/LCA.2026.3738639

Oğuz Ergin

引用次数: 0

SPIRE-HBM: A Sub-Pseudo-Channel Architecture for HBM4 Bandwidth Scaling SPIRE-HBM：用于HBM4带宽扩展的子伪信道架构

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-06-18 DOI: 10.1109/LCA.2026.3705360

Jungsul Lee;Eojin Lee

{"title":"SPIRE-HBM: A Sub-Pseudo-Channel Architecture for HBM4 Bandwidth Scaling","authors":"Jungsul Lee;Eojin Lee","doi":"10.1109/LCA.2026.3705360","DOIUrl":"https://doi.org/10.1109/LCA.2026.3705360","url":null,"abstract":"High-frequency HBM4 suffers from bandwidth underutilization because each pseudo channel (pCH) has only two bank groups within a selected Stack ID (SID), making BG interleaving insufficient to hide long column-to-column timing constraints. Existing industrial approaches mitigate this problem by adding DQ TSV resources, increasing implementation cost. We propose SPIRE-HBM, a sub-pseudo-channel-based HBM4 architecture that restores seamless BG-interleaved reads without increasing DQ TSVs. SPIRE-HBM partitions each 32-DQ pCH into two 16-DQ sub-pCH data paths across Stack IDs and doubles the burst length to preserve conventional access granularity. The longer burst provides sufficient column-command separation for two-BG interleaving, shifting the limiting column timing from <inline-formula><tex-math>$text{tCCD}_{text{L}}$</tex-math></inline-formula> to <inline-formula><tex-math>$text{tCCD}_{text{S}}$</tex-math></inline-formula>. Our evaluation shows that SPIRE-HBM improves performance by up to 1.10× for Llama3-8B and 1.15× for synthetic workloads over HBM4. In addition, at 12.8 Gbps, SPIRE-HBM achieves performance comparable to a TSV-doubled HBM4 baseline while retaining the DQ TSV count.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 2","pages":"263-266"},"PeriodicalIF":2.0,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DYCA-HBM: Accelerating Long-Context LLM on HBM-PIM With Dynamic Channel-Allocation DYCA-HBM：基于HBM-PIM的动态信道分配加速长上下文LLM

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-08-19 DOI: 10.1109/LCA.2026.3725787

Sangkyu Jeon;Jungsul Lee;Eojin Lee;Sungju Ryu

{"title":"DYCA-HBM: Accelerating Long-Context LLM on HBM-PIM With Dynamic Channel-Allocation","authors":"Sangkyu Jeon;Jungsul Lee;Eojin Lee;Sungju Ryu","doi":"10.1109/LCA.2026.3725787","DOIUrl":"https://doi.org/10.1109/LCA.2026.3725787","url":null,"abstract":"In long-context LLMs, attention is costly due to repeated accesses to a Key–Value (KV) cache. HBM-PIM can accelerate this memory-bound attention by leveraging its massive internal bandwidth. To effectively exploit this parallelism, prior PIM accelerators have proposed request-wise, head-wise, and block-wise KV-cache mappings to distribute attention workload across channels. However, these mapping schemes do not fully exploit the available internal bandwidth because they do not account for load changes caused by asynchronous request completion. To address this limitation, we propose DYCA-HBM, a dynamic channel allocation scheme that maintains balanced channel utilization across the entire decoding phase. DYCA-HBM tracks how each request’s KV is distributed across all channels. It maps new KV blocks to the least-loaded channel for load balancing, and prevents a single request’s blocks from excessively accumulating in specific channels. Experimental results show that DYCA-HBM improves throughput by up to 1.08× and 1.07× over AttAcc and BlockPIM, respectively, while reducing energy consumption by up to 7% with less than 0.07% logic-die area overhead.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 2","pages":"359-362"},"PeriodicalIF":2.0,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149033754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Taxonomy of SIMDe Emulation Inefficiencies for ARM NEON Porting of VVC Encoders ARM NEON移植VVC编码器的SIMDe仿真效率低下的分类

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-08-19 DOI: 10.1109/LCA.2026.3725622

Jeongkeun Kim

{"title":"A Taxonomy of SIMDe Emulation Inefficiencies for ARM NEON Porting of VVC Encoders","authors":"Jeongkeun Kim","doi":"10.1109/LCA.2026.3725622","DOIUrl":"https://doi.org/10.1109/LCA.2026.3725622","url":null,"abstract":"Compile-time x86<inline-formula><tex-math>$to$</tex-math></inline-formula>ARM SIMD translation via SIMDe is widely used to port intrinsic-heavy codebases to Neoverse-class cores, but its per-instruction translation scope leaves systematic architectural-asymmetry overhead uncharacterized in the architecture literature. We present a six-type taxonomy of SIMDe emulation inefficiencies— Redundant (R), Suboptimal (S), Widening (W), Fusion-miss (F), Memory (M), and Pipeline (P)—with assembly-level evidence for each type on AWS Graviton3 (Neoverse V1), organised under two underlying principles (per-instruction translation scope vs. architectural asymmetry). Using VVenC—the dominant open-source VVC encoder—as a case study, the taxonomy identifies 84 pattern instances across five SIMDe-dependent modules and guides native NEON implementations for three of them (DepQuant, Quant, TrQuant), achieving 1.22–1.40× encoder speedup (SIMDe-only to ours, Build A <inline-formula><tex-math>$to$</tex-math></inline-formula> C) and +0.4–+1.9% incremental gain over the upstream NEON port (Build B <inline-formula><tex-math>$to$</tex-math></inline-formula> C) on AWS Graviton3 and Graviton4 (medium preset, three sequences), with bit-exact output verified by MD5. The taxonomy is the primary contribution: a reusable diagnostic framework applicable to other SIMDe-using codebases targeting ARM.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 2","pages":"335-338"},"PeriodicalIF":2.0,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

HBM-HBF-Centric Memory Pooling Architecture With Custom Base Die for Terabyte-Scale LLM Inference 以hbm - hbf为中心的内存池架构，具有用于太字节规模LLM推理的自定义基础芯片

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-06-16 DOI: 10.1109/LCA.2026.3703982

Junho Park;Hyowon An;Haeseok Suh;Youngsu Yoon;Hyuni Lee;Joungho Kim

引用次数: 0

Exploring High-Bandwidth Flash for Modern LLM Inference: Opportunities and Challenges 探索现代法学硕士推理的高带宽闪存：机遇与挑战

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-06-22 DOI: 10.1109/LCA.2026.3705817

Dowon Son;Yonggon Park;Hyunuk Cho;Hyungkyu Ham;Onur Mutlu;Sungjin Lee;Gwangsun Kim;Jisung Park

引用次数: 0