pNet-gem5: Full-System Simulation With High-Performance Networking Enabled by Parallel Network Packet Processing

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Jongmin Shin;Seongtae Bang;Gyeongseo Park;Daehoon Kim
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引用次数: 0

Abstract

Modern server processors in data centers equipped with high-performance networking technologies (e.g., 100 Gigabit Ethernet) commonly support parallel packet processing via multi-queue NICs, enabling multiple cores to efficiently handle massive traffic loads. However, existing architectural simulators such as gem5 lack support for these techniques and suffer from limited bandwidth due to outdated networking models. Although a recent study introduced a simulation framework supporting userspace high-performance networking via the Data Plane Development Kit (DPDK), many applications still rely on kernel-based networking. To address these limitations, we present pNet-gem5, a full-system simulation framework designed to model server systems under high-performance network workloads, targeting data center architecture research. pNet-gem5 extends gem5 by supporting parallel packet processing on multi-core systems through the integration of multiple hardware queues and a more advanced interrupt mechanism—Message Signaled Interrupts (MSI)—which allows each NIC queue to be mapped to a dedicated core with its own IRQ. It also provides a high-performance network interface and device driver that support scalable and configurable packet distribution between hardware and software. Moreover, by decoupling packet distribution and scheduling from NIC core logic, pNet-gem5 enables flexible experimentation with custom policies. As a result, pNet-gem5 enables more realistic simulation of modern server environments by modeling multi-queue NICs and supporting bandwidths up to 46 Gbps—a significant improvement over the previous limit of only a few Gbps and more closely aligned with today’s tens-of-Gbps networks.
pNet-gem5:通过并行网络数据包处理实现高性能网络的全系统仿真
配备高性能网络技术(例如,100千兆以太网)的数据中心中的现代服务器处理器通常支持通过多队列网卡并行数据包处理,使多个核心能够有效地处理大量流量负载。然而,现有的架构模拟器(如gem5)缺乏对这些技术的支持,并且由于过时的网络模型而受到带宽限制。尽管最近的一项研究引入了一个模拟框架,通过数据平面开发工具包(Data Plane Development Kit, DPDK)支持用户空间高性能网络,但许多应用程序仍然依赖于基于内核的网络。为了解决这些限制,我们提出了pNet-gem5,这是一个全系统仿真框架,旨在对高性能网络工作负载下的服务器系统进行建模,目标是数据中心架构研究。pNet-gem5扩展了gem5,通过集成多个硬件队列和更高级的中断机制——消息信号中断(message signaling Interrupts, MSI)——在多核系统上支持并行数据包处理,MSI允许每个NIC队列被映射到具有自己IRQ的专用核心。它还提供了一个高性能的网络接口和设备驱动程序,支持硬件和软件之间可伸缩和可配置的数据包分发。此外,通过将数据包分发和调度与网卡核心逻辑解耦,pNet-gem5支持灵活的自定义策略实验。因此,pNet-gem5通过建模多队列nic并支持高达46 Gbps的带宽,从而能够更逼真地模拟现代服务器环境,这比以前仅为几Gbps的限制有了重大改进,并且与今天的数十Gbps网络更加接近。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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