Stardust: Scalable and Transferable Workload Mapping for Large AI on Multi-Chiplet Systems

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2025-06-17 DOI:10.1109/LCA.2025.3580562

Wencheng Zou;Feiyun Zhao;Nan Wu

引用次数: 0

Abstract

Workload partitioning and mapping are critical to optimizing performance in multi-chiplet systems. However, existing approaches struggle with scalability in large search spaces and lack transferability across different workloads. To overcome these limitations, we propose Stardust, a scalable and transferable workload mapping on multi-chiplet systems. Stardust combines learnable graph clustering to downscale computation graphs for efficient partitioning, topology-masked attention to capture structural information, and deep reinforcement learning (DRL) for optimized workload mapping. Evaluations on production-scale AI models show that (1) Stardust-generated mappings significantly outperform commonly used heuristics in throughput, and (2) fine-tuning a pre-trained Stardust model improves sample efficiency by up to 15× compared to training from scratch.

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星尘：多芯片系统上大型人工智能的可扩展和可转移工作负载映射

工作负载分区和映射是优化多芯片系统性能的关键。然而，现有的方法难以在大型搜索空间中实现可伸缩性，并且缺乏跨不同工作负载的可移植性。为了克服这些限制，我们提出了Stardust，一个可扩展和可转移的多芯片系统工作负载映射。Stardust结合了可学习的图聚类，以缩小计算图的规模，实现高效分区，拓扑掩码关注，捕获结构信息，深度强化学习（DRL），优化工作负载映射。对生产规模人工智能模型的评估表明：(1)Stardust生成的映射在吞吐量方面显著优于常用的启发式算法；(2)与从头开始训练相比，对预训练的Stardust模型进行微调可将样本效率提高15倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.