The Architectural Sustainability Indicator

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Jaime Roelandts;Ajeya Naithani;Lieven Eeckhout
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引用次数: 0

Abstract

Computing devices are responsible for a significant fraction of the world’s total carbon footprint. Designing sustainable systems is a challenging endeavor because of the huge design space, the complex objective function, and the inherent data uncertainty. To make matters worse, a design that seems sustainable at first, might turn out to not be when taking rebound effects into account. In this paper, we propose the Architectural Sustainability Indicator (ASI), a novel metric to assess the sustainability of a given design and determine whether it is strongly, weakly, or unsustainable. ASI provides insight and hints for turning unsustainable and weakly sustainable design points into strongly sustainable ones that are robust against potential rebound effects. A case study illustrates how ASI steers Scalar Vector Runahead, a weakly sustainable hardware prefetching technique, into a strongly sustainable one while offering a 3.2× performance boost.
建筑可持续发展指标
计算设备的碳足迹占世界总碳足迹的很大一部分。由于设计空间巨大,目标函数复杂,以及固有的数据不确定性,设计可持续系统是一项具有挑战性的工作。更糟糕的是,一开始看起来可持续的设计,在考虑反弹效应时可能会变得不可行。在本文中,我们提出了建筑可持续性指标(ASI),这是一种评估给定设计的可持续性并确定其是强、弱还是不可持续的新指标。ASI提供了将不可持续和弱可持续设计点转变为强可持续设计点的见解和提示,这些设计点可以抵御潜在的反弹效应。一个案例研究说明了ASI如何将一个弱可持续的硬件预取技术——标量矢量提前预取(Scalar Vector Runahead)转变为一个强可持续的技术,同时提供3.2倍的性能提升。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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