HINT: A Hardware Platform for Intra-Host NIC Traffic and SmartNIC Emulation

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2025-06-23 DOI:10.1109/LCA.2025.3582481

Jiaqi Lou;Yu Li;Srikar Vanavasam;Nam Sung Kim

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引用次数: 0

Abstract

Recent performance advancements in inter-host networking demand innovations in intra-host communication and SmartNIC-accelerated in-network processing. However, developing novel SmartNIC features remains difficult due to absence of hardware observability and low-cost, deterministic testing environments with existing software-based or commercial development platforms. While FPGA-based SmartNICs offer high flexibility and performance for packet processing acceleration, existing solutions support only a limited subset of network technologies widely used in commercial datacenters. To address these challenges, we introduce HINT, an FPGA-based development and emulation platform that transparently mimics a commercial SmartNIC in the system, featuring controlled network traffic generation with a high-performance traffic engine and kernel-bypass network technologies. It also supports configurable workload patterns, nanosecond-level latency measurement, and a reconfigurable Receive Side Scaling (RSS) engine for load balancing. Our evaluation shows that HINT achieves 91% of PCIe’s theoretical efficiency, providing a highly effective and scalable platform to emulate an end-to-end system with support for diverse network stacks. HINT thus establishes an accessible, high-fidelity platform for SmartNIC development and emulation, along with architectural exploration of intra-host communication.

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提示：主机内网卡流量和智能网卡仿真的硬件平台

最近主机间网络的性能进步要求在主机内通信和smartnic加速的网络处理方面进行创新。然而，由于缺乏硬件可观察性和现有基于软件或商业开发平台的低成本、确定性测试环境，开发新的SmartNIC功能仍然很困难。虽然基于fpga的smartnic为数据包处理加速提供了高灵活性和高性能，但现有的解决方案仅支持广泛用于商业数据中心的有限网络技术子集。为了应对这些挑战，我们引入了HINT，这是一个基于fpga的开发和仿真平台，它透明地模仿了系统中的商用SmartNIC，具有通过高性能流量引擎和内核旁路网络技术控制网络流量生成的特点。它还支持可配置的工作负载模式、纳秒级延迟测量和用于负载平衡的可重新配置的接收端缩放（RSS）引擎。我们的评估表明，HINT达到了PCIe理论效率的91%，提供了一个高效且可扩展的平台来模拟支持多种网络堆栈的端到端系统。因此，HINT为SmartNIC的开发和仿真建立了一个可访问的、高保真的平台，以及对主机内通信的架构探索。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.