IEEE Computer Architecture Letters最新文献_第10页

Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture 通过动态不对称架构提高深度神经网络训练效率

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-03-12 DOI: 10.1109/LCA.2023.3275909

Samer Kurzum;Gil Shomron;Freddy Gabbay;Uri Weiser

引用次数: 0

Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication 大整数多项式乘法的硬件实现轻量级加速器

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-03-10 DOI: 10.1109/LCA.2023.3274931

Pengzhou He;Yazheng Tu;Çetin Kaya Koç;Jiafeng Xie

引用次数: 0

In-Memory Versioning (IMV) 内存版本控制（IMV）

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-03-05 DOI: 10.1109/LCA.2023.3273124

David Andrew Roberts;Haojie Ye;Tony Brewer;Sean Eilert

引用次数: 0

Energy-Efficient Bayesian Inference Using Bitstream Computing 基于比特流计算的节能贝叶斯推理

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-02-14 DOI: 10.1109/LCA.2023.3238584

Soroosh Khoram;Kyle Daruwalla;Mikko Lipasti

引用次数: 0

Intelligent SSD Firmware for Zero-Overhead Journaling 用于零开销日志的智能SSD固件

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-02-09 DOI: 10.1109/LCA.2023.3243695

Hanyeoreum Bae;Donghyun Gouk;Seungjun Lee;Jiseon Kim;Sungjoon Koh;Jie Zhang;Myoungsoo Jung

引用次数: 0

Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching 存在野蛮预取时的最后一级缓存插入和提升策略

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-02-03 DOI: 10.1109/LCA.2023.3242178

Daniel A. Jiménez;Elvira Teran;Paul V. Gratz

引用次数: 2

ADT: Aggressive Demotion and Promotion for Tiered Memory ADT：分层内存的积极降级和升级

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-01-13 DOI: 10.1109/LCA.2023.3236685

Yaebin Moon;Wanju Doh;Kwanhee Kyung;Eojin Lee;Jung Ho Ahn

{"title":"ADT: Aggressive Demotion and Promotion for Tiered Memory","authors":"Yaebin Moon;Wanju Doh;Kwanhee Kyung;Eojin Lee;Jung Ho Ahn","doi":"10.1109/LCA.2023.3236685","DOIUrl":"10.1109/LCA.2023.3236685","url":null,"abstract":"Tiered memory using DRAM as upper-tier (fast memory) and emerging slower-but-larger byte-addressable memory as lower-tier (slow memory) is a promising approach to expanding main-memory capacity. Based on the observation that there are many cold pages in data-center applications, \u0000<italic>proactive demotion</i>\u0000 schemes demote cold pages to slow memory even when free space in fast memory is not deficient. Prior works on proactive demotion lower the requirement of expensive fast-memory capacity by reducing applications’ resident set size in fast memory. Also, some of the prior works mitigate the massive performance drop due to insufficient fast-memory capacity when there is a spike in demand for hot data. However, there is room for further improvement to save a larger fast-memory capacity with further aggressive demotion, which can fully reap the aforementioned advantages of proactive demotion. In this paper, we propose a new proactive demotion scheme, ADT, which performs \u0000<bold>a</b>\u0000ggressive \u0000<bold>d</b>\u0000emotion and promotion for \u0000<bold>t</b>\u0000iered memory. Using the memory access locality within the unit in which applications and memory allocators allocate memory, ADT extends the unit of demotion/promotion from the page adopted by prior works to make its demotion more aggressive. By performing demotion and promotion by the extended unit, ADT reduces 29% of fast-memory usage with only a 2.3% performance drop. Also, it achieves 2.28× speedup compared to the default Linux kernel when the system's memory usage is larger than fast-memory capacity, which outperforms state-of-the-art schemes for tiered memory management.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"22 1","pages":"21-24"},"PeriodicalIF":2.3,"publicationDate":"2023-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43125075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

HAMMER: Hardware-Friendly Approximate Computing for Self-Attention With Mean-Redistribution And Linearization HAMMER：具有均值重分布和线性化的自注意硬件友好近似计算

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-01-04 DOI: 10.1109/LCA.2022.3233832

Seonho Lee;Ranggi Hwang;Jongse Park;Minsoo Rhu

{"title":"HAMMER: Hardware-Friendly Approximate Computing for Self-Attention With Mean-Redistribution And Linearization","authors":"Seonho Lee;Ranggi Hwang;Jongse Park;Minsoo Rhu","doi":"10.1109/LCA.2022.3233832","DOIUrl":"10.1109/LCA.2022.3233832","url":null,"abstract":"The recent advancement of the natural language processing (NLP) models is the result of the ever-increasing model size and datasets. Most of these modern NLP models adopt the Transformer based model architecture, whose main bottleneck is exhibited in the self-attention mechanism. As the computation required for self-attention increases rapidly as the model size gets larger, self-attentions have been the main challenge for deploying NLP models. Consequently, there are several prior works which sought to address this bottleneck, but most of them suffer from significant design overheads and additional training requirements. In this work, we propose HAMMER, hardware-friendly approximate computing solution for self-attentions employing mean-redistribution and linearization, which effectively increases the performance of self-attention mechanism with low overheads. Compared to previous state-of-the-art self-attention accelerators, HAMMER improves performance by \u0000<inline-formula><tex-math>$1.2-1.6times$</tex-math></inline-formula>\u0000 and energy efficiency by \u0000<inline-formula><tex-math>$1.2-1.5times$</tex-math></inline-formula>\u0000.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"22 1","pages":"13-16"},"PeriodicalIF":2.3,"publicationDate":"2023-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47478009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures 基于运算集架构的fpga深度神经网络的超前编译

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2022-12-13 DOI: 10.1109/LCA.2022.3227643

Burkhard Ringlein;Francois Abel;Dionysios Diamantopoulos;Beat Weiss;Christoph Hagleitner;Dietmar Fey

引用次数: 1

CoreNap: Energy Efficient Core Allocation for Latency-Critical Workloads CoreNap：用于潜在关键工作负载的节能核心分配

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2022-12-08 DOI: 10.1109/LCA.2022.3227629

Gyeongseo Park;Ki-Dong Kang;Minho Kim;Daehoon Kim

{"title":"CoreNap: Energy Efficient Core Allocation for Latency-Critical Workloads","authors":"Gyeongseo Park;Ki-Dong Kang;Minho Kim;Daehoon Kim","doi":"10.1109/LCA.2022.3227629","DOIUrl":"10.1109/LCA.2022.3227629","url":null,"abstract":"In data-center servers, the dynamic core allocation for Latency-Critical (LC) applications can play a crucial role in improving energy efficiency under Service Level Objective (SLO) constraints, allowing cores to enter idle states (i.e., C-states) that consume less power by turning off a part of hardware components of a processor. However, prior studies focus on the core allocation for application threads while not considering cores involved in network packet processing, even though packet processing affects not only response latency but also energy consumption considerably. In this paper, we first investigate the impacts of the explicit core allocation for network packet processing on the tail response latency and energy consumption while running LC applications. We observe that co-adjusting the number of cores for network packet processing along with the number of cores for LC application threads can improve energy efficiency substantially, compared with adjusting the number of cores only for application threads, as prior studies do. In addition, we propose a dynamic core allocation, called \u0000<monospace>CoreNap</monospace>\u0000, which allocates/de-allocates cores for both LC application threads and packet processing. \u0000<monospace>CoreNap</monospace>\u0000 measures the CPU-utilization by application threads and packet processing individually, and predicts response latency and power consumption when the combination of core allocation is enforced via a lightweight prediction model. Based on the prediction, \u0000<monospace>CoreNap</monospace>\u0000 chooses/enforces the energy-efficient combination of core allocation. Our experimental results show that \u0000<monospace>CoreNap</monospace>\u0000 reduces energy consumption by up to 18.6% compared with state-of-the-art study that adjusts cores only for LC application in parallel packet processing environments.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"22 1","pages":"1-4"},"PeriodicalIF":2.3,"publicationDate":"2022-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42616181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0