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Towards Segmentation-Based Address Translation for LLM Inference 基于分段的LLM推理地址转换研究
IF 2 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-15 DOI: 10.1109/LCA.2026.3693796
Youngjoon Cheon;Yunho Oh;Jeongseob Ahn
{"title":"Towards Segmentation-Based Address Translation for LLM Inference","authors":"Youngjoon Cheon;Yunho Oh;Jeongseob Ahn","doi":"10.1109/LCA.2026.3693796","DOIUrl":"https://doi.org/10.1109/LCA.2026.3693796","url":null,"abstract":"As large language models (LLMs) continue to scale in both model size and context length, the efficiency of address translation has become a critical performance bottleneck during inference. Although LLM inference accesses model weights in a layer-wise pattern with substantial reuse across token generations, the expanding KV-cache footprint increasingly contends for TLB capacity, leaving fewer entries to cache weight translations. In this letter, we revisit segmentation-based address translation for model weights to bypass conventional TLB-based translation. Since model weights are read-only and not reclaimed for the lifetime of a serving instance, the segmentation-based address translation is well-suited to this access pattern. We place model weights in a virtually contiguous region backed by a physically contiguous memory, enabling segment-based translation that minimizes address translation overhead. Our evaluation shows that the proposed design improves overall IPC by 2.51 × over the paging baseline by achieving near-zero translation overhead for model weights.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"190-193"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148478975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PIAT: Unleashing Memory Parallelism via Power-Interference-Aware Timing Control PIAT：通过功率干扰感知定时控制释放内存并行性
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-06-02 DOI: 10.1109/LCA.2026.3699571
Yesin Ryu;Hyunjoon Kang;Jungrae Kim
{"title":"PIAT: Unleashing Memory Parallelism via Power-Interference-Aware Timing Control","authors":"Yesin Ryu;Hyunjoon Kang;Jungrae Kim","doi":"10.1109/LCA.2026.3699571","DOIUrl":"https://doi.org/10.1109/LCA.2026.3699571","url":null,"abstract":"Modern DRAM leverages bank-level parallelism to hide long access latency and sustain high throughput. However, shared on-die power resources restrict concurrent bank operations through timing parameters, which are set to uniform worst-case bounds even though power interference varies with the spatial relationship and concurrency of activations. This pessimism wastes parallelism and limits aggressive schemes such as Subarray-Level Parallelism (SALP). We propose Power-Interference-Aware Timing (PIAT), a timing control mechanism that adapts DRAM AC timing to expected power interference. PIAT selectively relaxes timing constraints based on physical separation and activation concurrency while preserving conservative timing for high-interference cases. This controller-side approach improves memory parallelism without DRAM hardware changes, achieving 0.8%–8.1% gains in the 32-bank configuration and 3.5%–88.9% in the 64-bank configuration across various SALP settings.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"214-217"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLA-TAGE: A Power-Efficient Branch Predictor With Vector-Loop Awareness 具有矢量环路感知能力的高能效支路预测器
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-02 DOI: 10.1109/LCA.2026.3669169
Chen Zhang;Shiqing Zhang;Guangda Zhang;Xiaobo Yan;Xia Zhao
{"title":"VLA-TAGE: A Power-Efficient Branch Predictor With Vector-Loop Awareness","authors":"Chen Zhang;Shiqing Zhang;Guangda Zhang;Xiaobo Yan;Xia Zhao","doi":"10.1109/LCA.2026.3669169","DOIUrl":"https://doi.org/10.1109/LCA.2026.3669169","url":null,"abstract":"Data-parallel workloads, such as machine learning, computer vision, and data analytics, increasingly run on mobile SoCs (System on Chip) with SIMD (Single Instruction, Multiple Data) engines to provide real-time user interactions and security. It is crucial to design processor architectures that balance high performance and power efficiency. In this paper, we make the key observation that these data-parallel workloads exhibit regular, predictable control flow, reducing the need for complex branch prediction mechanisms. However, state-of-the-art predictors like TAGE incur substantial power overhead due to multi-table lookups. In SIMD-intensive regions with long, regular loops, simpler prediction schemes can achieve comparable accuracy. Based on this insight, we propose Vector-Loop-Aware TAGE(VLA-TAGE), using a lightweight mechanism that dynamically gates access to TAGE tables during predictable SIMD execution while restoring full functionality for irregular control flow. VLA-TAGE maintains accuracy comparable to TAGE-SC-L while reducing the number of history table accesses by an average of 63%, resulting in a 51% reduction in power consumption on data-parallel workloads.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"105-109"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147557948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
LACIN: Linearly Arranged Complete Interconnection Networks LACIN：线性排列的完全互连网络
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2025-12-30 DOI: 10.1109/LCA.2025.3649284
Ramón Beivide;Cristóbal Camarero;Carmen Martínez;Enrique Vallejo;Mateo Valero
{"title":"LACIN: Linearly Arranged Complete Interconnection Networks","authors":"Ramón Beivide;Cristóbal Camarero;Carmen Martínez;Enrique Vallejo;Mateo Valero","doi":"10.1109/LCA.2025.3649284","DOIUrl":"https://doi.org/10.1109/LCA.2025.3649284","url":null,"abstract":"Several interconnection networks are based on the complete graph topology. Networks with a moderate size can be based on a single complete graph. However, large-scale networks such as Dragonfly and HyperX use, respectively, a hierarchical or a multi-dimensional composition of complete graphs. The number of links in these networks is huge and grows rapidly with their size. This paper introduces LACIN, a set of complete graph implementations that use identically indexed ports to link switches. This way of implementing the network reduces the complexity of its cabling and its routing. LACIN eases the deployment of networks for parallel computers of different scales, from VLSI systems to the largest supercomputers.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"29-32"},"PeriodicalIF":1.4,"publicationDate":"2025-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Inspex: Speculative Execution of Ready-to-Execute Loads in In-Order Cores Inspex：顺序核中准备执行负载的推测执行
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2025-12-26 DOI: 10.1109/LCA.2025.3646976
Yotaro Nada;Toru Koizumi;Ryota Shioya;Hidetsugu Irie;Shuichi Sakai
{"title":"Inspex: Speculative Execution of Ready-to-Execute Loads in In-Order Cores","authors":"Yotaro Nada;Toru Koizumi;Ryota Shioya;Hidetsugu Irie;Shuichi Sakai","doi":"10.1109/LCA.2025.3646976","DOIUrl":"https://doi.org/10.1109/LCA.2025.3646976","url":null,"abstract":"In-order (InO) cores are processor cores that execute instructions in program order. Due to their low complexity, InO cores have been widely used in situations where energy efficiency and small circuit area are required, but they provide limited performance. We focus on stalls in InO cores that are caused by load instructions and their consumer instructions. These stalls significantly degrade the performance, which accounts for 70% of the total execution time on SPEC CPU 2017. We found that many of these load instructions are ready to execute and could have been issued earlier. Based on this observation, we propose Inspex, which improves the performance of InO cores while maintaining its simplicity. Inspex predicts ready-to-execute loads and speculatively pre-executes them. This enables obtaining load results earlier, thereby removing the stalls caused by load consumers. Our simulation results show that Inspex improved the performance by 25.6% and reduced the energy consumption by 10.6%, and reduced the energy-delay product by 28.0% compared with a baseline InO core while incurring an area overhead of 0.65%.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"17-20"},"PeriodicalIF":1.4,"publicationDate":"2025-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11316409","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enabling Cost-Efficient LLM Inference on Mid-Tier GPUs With NMP DIMMs 在采用NMP内存条的中间层gpu上实现低成本LLM推理
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2025-12-22 DOI: 10.1109/LCA.2025.3646622
Heewoo Kim;Alan La;Joseph Izraelevitz
{"title":"Enabling Cost-Efficient LLM Inference on Mid-Tier GPUs With NMP DIMMs","authors":"Heewoo Kim;Alan La;Joseph Izraelevitz","doi":"10.1109/LCA.2025.3646622","DOIUrl":"https://doi.org/10.1109/LCA.2025.3646622","url":null,"abstract":"Large Language Models (LLMs) require substantial computational resources, making cost-efficient inference challenging. Scaling out with mid-tier GPUs (e.g., NVIDIA A10) appears attractive for LLMs, but our characterization shows that communication bottlenecks prevent them from matching high-end GPUs (e.g., 4 × A100). Using 16 × A10 GPUs, we find the decode stage—dominant in inference runtime—is memory-bandwidth-bound in matrix multiplications, I/O-bandwidth-bound in <italic>AllReduce</i>, and underutilizes compute resources. These traits make it well-suited for both DIMM-based Near-Memory Processing (NMP) offloading and also communication quantization. Analytical modeling shows that a 16 × A10 with NMP DIMMs and INT8 communication quantization can match 4 × A100 performance at 30% lower cost and even surpass it under equal cost. These results demonstrate the potential of our approach for cost-efficient LLM inference on mid-tier GPUs.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"21-24"},"PeriodicalIF":1.4,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Understanding the Performance Behaviors of End-to-End Protein Design Pipelines on GPUs 了解gpu上端到端蛋白质设计管道的性能行为
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2025-12-19 DOI: 10.1109/LCA.2025.3646250
Jinwoo Hwang;Yeongmin Hwang;Tadiwos Meaza;Hyeonbin Bae;Jongse Park
{"title":"Understanding the Performance Behaviors of End-to-End Protein Design Pipelines on GPUs","authors":"Jinwoo Hwang;Yeongmin Hwang;Tadiwos Meaza;Hyeonbin Bae;Jongse Park","doi":"10.1109/LCA.2025.3646250","DOIUrl":"https://doi.org/10.1109/LCA.2025.3646250","url":null,"abstract":"Recent computational advances enable protein design pipelines to run end-to-end on GPUs, yet their heterogeneous computational behaviors remain undercharacterized at the system level. We implement and profile a representative pipeline at both component and full-pipeline granularities across varying inputs and hyperparameters. Our characterization identifies generally low GPU utilization and high sensitivity to sequence length and sampling strategies. We outline future research directions based on these insights and release an open-source pipeline and profiling scripts to facilitate further studies.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"9-12"},"PeriodicalIF":1.4,"publicationDate":"2025-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Exploring KV Cache Quantization in Multimodal Large Language Model Inference 探索多模态大语言模型推理中的KV缓存量化
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2025-12-19 DOI: 10.1109/LCA.2025.3646170
Hyesung Ahn;Ranggi Hwang;Minsoo Rhu
{"title":"Exploring KV Cache Quantization in Multimodal Large Language Model Inference","authors":"Hyesung Ahn;Ranggi Hwang;Minsoo Rhu","doi":"10.1109/LCA.2025.3646170","DOIUrl":"https://doi.org/10.1109/LCA.2025.3646170","url":null,"abstract":"Multimodal large language models (MLLMs) have demonstrated strong performance across modalities, such as image, video, and audio understanding, by leveraging large language models (LLMs) as a backbone. However, a critical challenge in MLLM inference is the large memory capacity required for the key–value (KV) cache, particularly when processing high-resolution images. This pressure often forces heterogeneous CPU–GPU systems to offload the KV cache to CPU memory, introducing substantial transfer latency. KV cache quantization is a promising way to reduce this memory demand, yet it remains underexplored for MLLM inference. In this work, we characterize MLLM inference and present a text-centric KV cache quantization method that retains only 10% of tokens in high precision while quantizing the rest. Our method reduces Time-To-First-Token (TTFT) by <inline-formula><tex-math>$1.7times$</tex-math></inline-formula> and Time-Per-Output-Token (TPOT) by <inline-formula><tex-math>$4.3times$</tex-math></inline-formula>, with negligible accuracy loss.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"13-16"},"PeriodicalIF":1.4,"publicationDate":"2025-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CrossFetch: A Prefetching Scheme for Cross-Page Prefetching in the Physical Address Space 交叉取：一种在物理地址空间中进行跨页预取的预取方案
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2025-12-08 DOI: 10.1109/LCA.2025.3640965
Qi Shao;Per Stenstrom
{"title":"CrossFetch: A Prefetching Scheme for Cross-Page Prefetching in the Physical Address Space","authors":"Qi Shao;Per Stenstrom","doi":"10.1109/LCA.2025.3640965","DOIUrl":"https://doi.org/10.1109/LCA.2025.3640965","url":null,"abstract":"Prefetching is an important technique to reduce the miss penalty in deep memory hierarchies, employing multiple levels of cache and memory. Unfortunately, state-of-the-art techniques avoid prefetching across page boundaries in physically addressed memory because contiguous virtual pages are not guaranteed to map to contiguous physical pages. Apart from low accuracy, prefetching across page boundaries can break protection domains, opening up security vulnerabilities. This paper proposes CrossFetch — the first prefetching technique that accurately and securely prefetches data across physical page boundaries. It uses a simple and novel translation mechanism that combines a conventional TLB, called forward TLB (FTLB), with a reverse TLB (RTLB) that provides mappings of physical pages to virtual. CrossFetch leverages a conventional Page Table Walker invoked by a conventional TLB to load mappings into the FTLB and RTLB. The paper demonstrates how CrossFetch can hide far-memory misses in hybrid main-memory systems and last-level cache misses. We show that CrossFetch can improve IPC by 5.7% (up to 27.7%) compared to intra-page prefetchers on SPEC2017 benchmarks where the tolerance of far-memory misses dominates.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"1-4"},"PeriodicalIF":1.4,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11282456","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145860191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
LeakDiT: Diffusion Transformers for Trace-Augmented Side-Channel Analysis 用于迹线增强侧通道分析的扩散变压器
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2025-12-02 DOI: 10.1109/LCA.2025.3639372
Insup Lee;Daehyeon Bae;Seokhie Hong;Sangjin Lee
{"title":"LeakDiT: Diffusion Transformers for Trace-Augmented Side-Channel Analysis","authors":"Insup Lee;Daehyeon Bae;Seokhie Hong;Sangjin Lee","doi":"10.1109/LCA.2025.3639372","DOIUrl":"https://doi.org/10.1109/LCA.2025.3639372","url":null,"abstract":"Deep learning has been extensively used in side-channel analysis (SCA), making trace data insufficiency and class imbalance a critical challenge. Although several studies have explored trace augmentation with generative models, two core limitations remain: (i) insufficient integration of SCA domain knowledge into the models and (ii) limited adoption of state-of-the-art diffusion transformers (DiT). This letter presents <sc>LeakDiT</small>, a domain-specific one-dimensional DiT that generates high-quality traces. <sc>LeakDiT</small> introduces a loss based on normalized inter-class variance (NICV) to produce realistic traces that preserve the leakage structure. Experimental results demonstrate that <sc>LeakDiT</small> improves SCA performance and reduces the number of required traces for key recovery.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"5-8"},"PeriodicalIF":1.4,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145861219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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