IEEE Computer Architecture Letters最新文献_第9页

Kobold: Simplified Cache Coherence for Cache-Attached Accelerators Kobold：简化缓存连接加速器的缓存一致性

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-04-21 DOI: 10.1109/LCA.2023.3269399

Jennifer Brana;Brian C. Schwedock;Yatin A. Manerkar;Nathan Beckmann

{"title":"Kobold: Simplified Cache Coherence for Cache-Attached Accelerators","authors":"Jennifer Brana;Brian C. Schwedock;Yatin A. Manerkar;Nathan Beckmann","doi":"10.1109/LCA.2023.3269399","DOIUrl":"10.1109/LCA.2023.3269399","url":null,"abstract":"The ever-increasing cost of data movement in computer systems is driving a new era of data-centric computing. One of the most common data-centric paradigms is near-data computing (NDC), where accelerators are placed \u0000<italic>inside</i>\u0000 the memory hierarchy to avoid the costly transfer of data to the core. NDC systems show immense potential to improve performance and energy efficiency. Unfortunately, adding accelerators into the memory hierarchy incurs significant complexity for system integration because accelerators often require cache-coherent access to memory. The complex coherence protocols required to handle both cores and cache-attached accelerators result in significantly higher verification costs as well as an increase in directory state and on-chip network traffic. Furthermore, these mechanisms can cause cache pollution and worsen baseline processor performance. To simplify the integration of cache-attached accelerators, we present Kobold, a new coherence protocol and implementation which restricts the added complexity of an accelerator to its local tile. Kobold introduces a new directory structure within the L2 cache to track the accelerator's private cache and maintain coherence between the core and accelerator. A minor modification to the LLC protocol also enables accelerators to improve performance by bypassing the local L2. We verified Kobold's stable-state coherence protocols using the Murphi model checker and estimated area overhead using Cacti 7. Kobold simplifies integration of cache-attached accelerators, adds only 0.09% area over the baseline caches, and provides clear performance advantages versus naïve extensions of existing directory coherence protocols.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43340299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays Canal:用于粗粒度可重构阵列的柔性互连生成器

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-04-19 DOI: 10.1109/LCA.2023.3268126

Jackson Melchert;Keyi Zhang;Yuchen Mei;Mark Horowitz;Christopher Torng;Priyanka Raina

{"title":"Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays","authors":"Jackson Melchert;Keyi Zhang;Yuchen Mei;Mark Horowitz;Christopher Torng;Priyanka Raina","doi":"10.1109/LCA.2023.3268126","DOIUrl":"10.1109/LCA.2023.3268126","url":null,"abstract":"The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power, performance, and area. Design decisions that have complex trade-offs need to be explored to maintain efficiency and performance across a variety of evolving applications. This paper presents Canal, a Python-embedded domain-specific language (eDSL) and compiler for specifying and generating reconfigurable interconnects for CGRAs. Canal uses a graph-based intermediate representation (IR) that allows for easy hardware generation and tight integration with place and route tools. We evaluate Canal by constructing both a fully static interconnect and a hybrid interconnect with ready-valid signaling, and by conducting design space exploration of the interconnect architecture by modifying the switch box topology, the number of routing tracks, and the interconnect tile connections. Through the use of a graph-based IR for CGRA interconnects, the eDSL, and the interconnect generation system, Canal enables fast design space exploration and creation of CGRA interconnects.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43724888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

SmartIndex: Learning to Index Caches to Improve Performance SmartIndex:学习索引缓存以提高性能

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-04-05 DOI: 10.1109/LCA.2023.3264478

Kevin Weston;Farabi Mahmud;Vahid Janfaza;Abdullah Muzahid

引用次数: 0

An Intermediate Language for General Sparse Format Customization 通用稀疏格式自定义的中间语言

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-03-28 DOI: 10.1109/LCA.2023.3262610

Jie Liu;Zhongyuan Zhao;Zijian Ding;Benjamin Brock;Hongbo Rong;Zhiru Zhang

{"title":"An Intermediate Language for General Sparse Format Customization","authors":"Jie Liu;Zhongyuan Zhao;Zijian Ding;Benjamin Brock;Hongbo Rong;Zhiru Zhang","doi":"10.1109/LCA.2023.3262610","DOIUrl":"https://doi.org/10.1109/LCA.2023.3262610","url":null,"abstract":"The inevitable trend of hardware specialization drives an increasing use of custom data formats in processing sparse workloads, which are typically memory-bound. These formats facilitate the automated generation of target-aware data layouts to improve memory access latency and bandwidth utilization. However, existing sparse tensor programming models and compilers offer little or no support for productively customizing the sparse formats. Moreover, since these frameworks adopt an attribute-based approach for format abstraction, they cannot easily be extended to support general format customization. To overcome this deficiency, we propose UniSparse, an intermediate language that provides a unified abstraction for representing and customizing sparse formats. We also develop a compiler leveraging the MLIR infrastructure, which supports adaptive customization of formats. We demonstrate the efficacy of our approach through experiments running commonly-used sparse linear algebra operations with hybrid formats on multiple different hardware targets, including an Intel CPU, an NVIDIA GPU, and a simulated processing-in-memory (PIM) device.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49962233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

XLA-NDP: Efficient Scheduling and Code Generation for Deep Learning Model Training on Near-Data Processing Memory XLA-NDP：用于近数据处理存储器上的深度学习模型训练的高效调度和代码生成

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-03-23 DOI: 10.1109/LCA.2023.3261136

Jueon Park;Hyojin Sung

引用次数: 0

Towards Improved Power Management in Cloud GPUs 改进云gpu的电源管理

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-03-22 DOI: 10.1109/LCA.2023.3278652

Pratyush Patel;Zibo Gong;Syeda Rizvi;Esha Choukse;Pulkit Misra;Thomas Anderson;Akshitha Sriraman

引用次数: 4

The Jaseci Programming Paradigm and Runtime Stack: Building Scale-Out Production Applications Easy and Fast Jaseci编程范式和运行时堆栈:构建横向扩展的生产应用程序容易和快速

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-03-18 DOI: 10.1109/LCA.2023.3274038

Jason Mars;Yiping Kang;Roland Daynauth;Baichuan Li;Ashish Mahendra;Krisztian Flautner;Lingjia Tang

引用次数: 0

Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping 利用LLC重映射缓解基于定时的NoC侧信道攻击

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-03-16 DOI: 10.1109/LCA.2023.3276709

Anurag Kar;Xueyang Liu;Yonghae Kim;Gururaj Saileshwar;Hyesoon Kim;Tushar Krishna

引用次数: 0

RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs RouteReplies：缓解多芯片模块GPU的长延迟

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-03-13 DOI: 10.1109/LCA.2023.3255555

Xia Zhao;Guangda Zhang;Lu Wang;Yangmei Li;Yongjun Zhang

引用次数: 0

Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture 通过动态不对称架构提高深度神经网络训练效率

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-03-12 DOI: 10.1109/LCA.2023.3275909

Samer Kurzum;Gil Shomron;Freddy Gabbay;Uri Weiser

引用次数: 0