发布求助
文献互助 智能选刊 最新文献

IEEE Computer Architecture Letters最新文献

筛选
英文 中文
Nighthawk: Zero-Copy Cache Quarantine for Invisible Speculation 夜鹰：用于不可见推测的零副本缓存隔离
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-25 DOI: 10.1109/LCA.2026.3677441
Minwoo Jang;Sungju Kim;Daehoon Kim
{"title":"Nighthawk: Zero-Copy Cache Quarantine for Invisible Speculation","authors":"Minwoo Jang;Sungju Kim;Daehoon Kim","doi":"10.1109/LCA.2026.3677441","DOIUrl":"https://doi.org/10.1109/LCA.2026.3677441","url":null,"abstract":"Out-of-order execution enhances processor performance but introduces transient execution vulnerabilities that leak confidential data via microarchitectural side effects. Existing defenses often necessitate invasive hardware modifications—such as dedicated buffers or complex forwarding logic—resulting in prohibitive performance degradation. We propose <monospace>Nighthawk</monospace>, a lightweight defense that repurposes existing cache ways to isolate speculative loads without the area overhead of auxiliary structures. <monospace>Nighthawk</monospace> introduces an in-cache quarantine mechanism that dynamically allocates a specific cache way to buffer speculative data, effectively eliminating the data-copy latency inherent in decoupled buffer designs. By integrating this mechanism with Speculative Taint Tracking (STT), we transform STT’s restrictive stall policy into a prefetch-but-quarantine strategy. This approach recovers memory-level parallelism by allowing speculative misses to proceed into the quarantined way while blocking microarchitectural propagation until resolution. Evaluation using gem5 on SPEC CPU2006/2017 benchmarks demonstrates that <monospace>Nighthawk</monospace> reclaims performance lost to STT, reducing execution time by 6.2% on average and up to 28.8% for memory-intensive workloads, offering a more practical design point for secure high-performance processors.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"134-137"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147737037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ReplayOpt: Optimizer-State Replay to Resolve Critical-Path Bottlenecks in Offloaded Training ReplayOpt：优化器状态重播，以解决卸载训练中的关键路径瓶颈
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-23 DOI: 10.1109/LCA.2026.3676470
Seongtae Bang;Gyeongseo Park;Kyeonghyeon Ryu;Daehoon Kim
{"title":"ReplayOpt: Optimizer-State Replay to Resolve Critical-Path Bottlenecks in Offloaded Training","authors":"Seongtae Bang;Gyeongseo Park;Kyeonghyeon Ryu;Daehoon Kim","doi":"10.1109/LCA.2026.3676470","DOIUrl":"https://doi.org/10.1109/LCA.2026.3676470","url":null,"abstract":"CPU-offloaded training enables billion-scale model training on modest GPU clusters by storing high-precision optimizer state in host memory while keeping low-precision weights on the GPU. We find that CPU-offloaded training is often bottlenecked not by PCIe transfers but by storing high-precision optimizer state in host memory, which delays the next iteration and stalls the GPU. In our measurements, these non-overlapped stores account for up to 28% of CPU-side optimizer time and delay the start of the next iteration, leaving the GPU idle. We propose <italic>ReplayOpt</i>, an optimizer design that reorders the CPU–GPU update schedule to remove host memory state stores from the critical path. <italic>ReplayOpt</i> produces and transfers the next-iteration low-precision weights first and replays high-precision state updates in the background to remove host memory writebacks from the critical path. Across LLM workloads, <italic>ReplayOpt</i> reduces CPU-side optimizer time by up to 55.2% and step time by up to 21.7% without accuracy loss.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"142-145"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147737048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sāmaya: Safe Memory Accesses to Expand Coarse-Grain Reconfigurable Array Adoption Sāmaya：安全内存访问扩展粗粒度可重构阵列的采用
IF 2 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-06-08 DOI: 10.1109/LCA.2026.3701336
Alex Coppens;Jeremy Sha;Milijana Surbatovich;Bahar Asgari
{"title":"Sāmaya: Safe Memory Accesses to Expand Coarse-Grain Reconfigurable Array Adoption","authors":"Alex Coppens;Jeremy Sha;Milijana Surbatovich;Bahar Asgari","doi":"10.1109/LCA.2026.3701336","DOIUrl":"https://doi.org/10.1109/LCA.2026.3701336","url":null,"abstract":"Coarse-grain reconfigurable architectures (CGRAs) offer an attractive tradeoff between performance, energy efficiency, and flexibility, making them promising accelerators for loop-intensive workloads. However, their adoption is hindered by limited support for safe execution. Existing CGRA toolchains primarily compile kernels written in C, inheriting C’s lack of memory safety. While unsafe memory accesses on CPUs may be detected by hardware or the OS, equivalent accesses on CGRAs can occur silently, with little visibility into such errors during execution. Our key insight is that Rust’s safety and error-handling semantics can be leveraged when mapping kernels to CGRAs. Rust’s compile-time guarantees and lightweight runtime checks make it well suited to addressing memory safety challenges in dataflow architectures. To enable safe memory accesses, we propose Sāmaya, a CGRA compilation and execution framework that integrates a Rust-based compilation pipeline into the open-source CGRA compilation framework Morpher, extends dataflow graph generation with safety metadata and multiple error exits, and propagates this information through widened datapaths and registers. We implement Sāmaya on the HyCUBE CGRA architecture and evaluate it using a diverse set of kernels.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"226-229"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
EONSim: An NPU Simulator for On-Chip Memory and Embedding Vector Operations 用于片上存储器和嵌入向量操作的NPU模拟器
IF 2 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-02-24 DOI: 10.1109/LCA.2026.3667792
Sangun Choi;Jongmin Kim;Jaeyong Park;Yunho Oh
{"title":"EONSim: An NPU Simulator for On-Chip Memory and Embedding Vector Operations","authors":"Sangun Choi;Jongmin Kim;Jaeyong Park;Yunho Oh","doi":"10.1109/LCA.2026.3667792","DOIUrl":"https://doi.org/10.1109/LCA.2026.3667792","url":null,"abstract":"Embedding vector operations account for a growing share of modern deep neural network workloads and exhibit input-dependent and highly skewed memory access behavior. This behavior arises from runtime index sequences, in contrast to the static loop structure of matrix operation-centric kernels. Existing neural processing unit (NPU) simulators primarily target matrix operations and derive memory accesses from tiling and scheduling logic, which limits fidelity for embedding-heavy workloads. Also, coarse on-chip memory abstractions based on aggregate bandwidth and transfer latency hinder analysis of reuse behavior and both software- and hardware-managed on-chip memory techniques. This paper presents EONSim, an embedding-aware NPU simulator that captures index-driven memory behavior. EONSim represents embedding workloads through reusable, hardware-agnostic index traces and integrates a detailed on-chip memory model that supports diverse management policies, including software prefetching and hardware caching. Across multiple NPU configurations, EONSim reports an average inference time error of 1.3% and an average on-chip memory access count error of 5.5%.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"73-76"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148478864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CGR-NPU: A Hybrid CGRA and NPU Architecture for Adaptive Neural Computing Workloads CGR-NPU：一种用于自适应神经计算工作负载的CGRA和NPU混合架构
IF 2 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2025-12-24 DOI: 10.1109/LCA.2025.3647885
Junzhe Jing;Feng Min;Yiming Gan;Ying Wang;Yinhe Han
{"title":"CGR-NPU: A Hybrid CGRA and NPU Architecture for Adaptive Neural Computing Workloads","authors":"Junzhe Jing;Feng Min;Yiming Gan;Ying Wang;Yinhe Han","doi":"10.1109/LCA.2025.3647885","DOIUrl":"https://doi.org/10.1109/LCA.2025.3647885","url":null,"abstract":"To exploit apabilities of processors in contemporary heterogeneous systems, frequent data movement across disparate memory domains is required. The substantial overhead incurred by this data transfer is now a principal bottleneck for system performance, especially for computationally intensive, large-scale AI workloads. To address this, we propose CGR-NPU, a hybrid architecture that synergistically combines a Coarse-Grained Reconfigurable Array (CGRA) with a Neural Processing Unit (NPU). The architecture features tightly-coupled CGRA and NPU operational modes with fast switching, and leverages a reinforcement learning-based mechanism for dynamic resource allocation tailored to workload characteristics. Evaluations on diverse ML benchmarks show our integrated architecture improves average 1.62× performance speed up and reduces silicon area by 48.4% compared to standalone CGRA or NPU baselines. The overhead for mode switching and internal data handling is minimal, constituting only 7% of the total execution time.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"81-84"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148478735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterizing Carbon Cost of Federated Learning 表征联邦学习的碳成本
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-04-03 DOI: 10.1109/LCA.2026.3680611
Yonglak Son;Chanwoo Cho;Seongbin Park;Young Seo Lee;Young Geun Kim
{"title":"Characterizing Carbon Cost of Federated Learning","authors":"Yonglak Son;Chanwoo Cho;Seongbin Park;Young Seo Lee;Young Geun Kim","doi":"10.1109/LCA.2026.3680611","DOIUrl":"https://doi.org/10.1109/LCA.2026.3680611","url":null,"abstract":"Federated learning (FL) is a decentralized learning approach for training machine learning models without sharing user data with a centralized server. Though FL is considered as a practical solution to mitigate the risk of privacy leakage in training, its environmental impact can be significant, especially considering the scale of billions of mobile users. In this letter, we first demonstrate the carbon cost of privacy by quantifying and characterizing the carbon footprint (CF) of FL while accounting for both server-side FL settings and client heterogeneity. Our analysis reveals that CF-optimal FL settings vary by the service-level objective, and client heterogeneity further complicates CF optimization of FL. We believe our work will be a practical guideline for designing carbon-efficient FL systems.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"150-153"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147737019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FlowFlash: An Efficient Dataflow Strategy for FlashAttention Execution on Systolic Arrays FlowFlash：一种有效的数据流策略，用于收缩阵列上的FlashAttention执行
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-30 DOI: 10.1109/LCA.2026.3678312
Baosen Wang;Junjie Wang;Siyu Xiao;Y. Liu
{"title":"FlowFlash: An Efficient Dataflow Strategy for FlashAttention Execution on Systolic Arrays","authors":"Baosen Wang;Junjie Wang;Siyu Xiao;Y. Liu","doi":"10.1109/LCA.2026.3678312","DOIUrl":"https://doi.org/10.1109/LCA.2026.3678312","url":null,"abstract":"To tackle the severe underutilization of systolic arrays in FlashAttention, we propose FlowFlash, a dataflow strategy employing Inter-Block Overlap and Unroll techniques. By fusing three consecutive blocks into a single hardware loop to eliminate pipeline stalls, FlowFlash achieves 85.8% FLOPs/s utilization. This represents a 2.10x–10.14x improvement over state-of-the-art systolic array-based accelerators, while maintaining high area and power efficiency.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"138-141"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147737113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-Bandwidth Flash for KV Caches: Endurance and Performance Implications 用于KV缓存的高带宽闪存：耐久性和性能影响
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-22 DOI: 10.1109/LCA.2026.3695938
Kwanhee Kyung;Yeon Ji Moon;Juhwan Cho;Jung Ho Ahn
{"title":"High-Bandwidth Flash for KV Caches: Endurance and Performance Implications","authors":"Kwanhee Kyung;Yeon Ji Moon;Juhwan Cho;Jung Ho Ahn","doi":"10.1109/LCA.2026.3695938","DOIUrl":"https://doi.org/10.1109/LCA.2026.3695938","url":null,"abstract":"During Large Language Model (LLM) inference, the key-value (KV) cache is a critical bottleneck in both capacity and memory bandwidth as context lengths surge. While High-Bandwidth Memory (HBM) can meet current bandwidth demands, its capacity has not kept pace with the rapidly growing footprint of the KV cache. Consequently, KV caches are frequently offloaded to CPU memory for higher capacity, yet performance remains constrained by limited interconnect bandwidth. High-Bandwidth Flash (HBF) has emerged as a promising alternative, offering sequential read bandwidth comparable to HBM4 with up to an order-of-magnitude higher capacity. Although Flash memory has limited write endurance, KV caches exhibit a favorable access pattern, being written once and read many times during inference. Our analysis demonstrates that the KV cache read-to-write ratio increases with longer context lengths, particularly with larger output sequences. This characteristic enables KV caches to be stored in HBF while maintaining an acceptable device lifetime, addressing both the capacity and bandwidth challenges of contemporary LLM systems.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"210-213"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient MoE Model Fine-Tuning on Commodity GPU Server With Offloading 基于GPU服务器卸载的高效MoE模型微调
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-31 DOI: 10.1109/LCA.2026.3679296
Yu-Hu Kuo;Hung-Tso Shiao;Chia-Lin Yang
{"title":"Efficient MoE Model Fine-Tuning on Commodity GPU Server With Offloading","authors":"Yu-Hu Kuo;Hung-Tso Shiao;Chia-Lin Yang","doi":"10.1109/LCA.2026.3679296","DOIUrl":"https://doi.org/10.1109/LCA.2026.3679296","url":null,"abstract":"Fine-tuning enables the efficient adaptation of pre-trained models on commodity GPUs but is constrained by the memory capacity. To mitigate this, recent systems combine model parallelism with CPU–GPU offloading. We focus on fine-tuning Mixture-of-Experts (MoE) models on commodity GPU server using layer-wise offloading and expert parallelism (EP). However, EP-based MoE training suffers from significant load imbalance because the gating network routes tokens unevenly among experts. To address this load imbalance issue, we propose a Prediction-based Dynamic Expert Placement (PDEP) framework. By employing a layer-wise workload predictor, PDEP utilizes the CPU-to-GPU weight transfer to dynamically adjust expert assignments. Our method reduces GPU idle time, achieves near-balanced workload distribution, and delivers up to 1.49× end-to-end speedup over static expert placement.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"178-181"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
LWAL: Lightweight Adaptive Learning-Driven Cache Bypassing for GPUs LWAL: gpu的轻量级自适应学习驱动缓存旁路
IF 1.4 3区 计算机科学
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-11 DOI: 10.1109/LCA.2026.3673140
Cong Thuan Do
{"title":"LWAL: Lightweight Adaptive Learning-Driven Cache Bypassing for GPUs","authors":"Cong Thuan Do","doi":"10.1109/LCA.2026.3673140","DOIUrl":"https://doi.org/10.1109/LCA.2026.3673140","url":null,"abstract":"Modern GPUs play a crucial role in accelerating general-purpose applications. However, these applications often involve frequent off-chip memory accesses with high latencies. Although GPUs incorporate a memory hierarchy with various caches to alleviate this problem, limited cache capacity and suboptimal management of irregular access patterns often diminish their effectiveness. In many cases, these small caches even become performance bottlenecks, negatively impacting the execution of general-purpose applications. To address these challenges, we propose a cache bypassing scheme that is driven by a lightweight adaptive learning (called LWAL). Experimental results across a range of workloads demonstrate that the proposed LWAL scheme delivers an average performance improvement of 22.5%.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"110-113"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147557655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书