对 ATD 标签进行散列处理，实现低开销的安全争用监测

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2024-03-15 DOI:10.1109/LCA.2024.3401570

Pablo Andreu;Pedro Lopez;Carles Hernandez

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引用次数: 0

摘要

通过引入多核处理器来提高安全关键型系统的性能已成为一种常态。然而，当多个内核访问一个共享缓存时，内核间的驱逐就会成为一个相关的干扰源，必须加以适当控制。为了解决这个问题，我们可以静态划分高速缓存并消除干扰。遗憾的是，这样做的代价是灵活性降低，在某些情况下性能更差。在这种情况下，要实现更灵活的缓存分配策略，就需要额外的监控支持。本文提出的 HashTAG 是一种新颖的方法，可以准确地确定内核间驱逐干扰的上限。HashTAG 可以低开销地实现辅助标签目录，以确定内核间驱逐。我们的研究结果表明，使用 HashTAG 不会出现任务间干扰预测不足的情况，同时 ATD 面积减少了 44%，中位数预测过度率仅为 1.14%。

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Hashing ATD Tags for Low-Overhead Safe Contention Monitoring

Increasing the performance of safety-critical systems via introducing multicore processors is becoming the norm. However, when multiple cores access a shared cache, inter-core evictions become a relevant source of interference that must be appropriately controlled. To solve this issue, one can statically partition caches and remove the interference. Unfortunately, this comes at the expense of less flexibility and, in some cases, worse performance. In this context, enabling more flexible cache allocation policies requires additional monitoring support. This paper proposes HashTAG, a novel approach to accurately upper-bound inter-core eviction interference. HashTAG enables a low-overhead implementation of an Auxiliary Tag Directory to determine inter-core evictions. Our results show that no inter-task interference underprediction is possible with HashTAG while providing a 44% reduction in ATD area with only 1.14% median overprediction.

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.