Analysis of Data Transfer Bottlenecks in Commercial PIM Systems: A Study With UPMEM-PIM

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2024-04-12 DOI:10.1109/LCA.2024.3387472

Dongjae Lee;Bongjoon Hyun;Taehun Kim;Minsoo Rhu

引用次数: 0

Abstract

Due to emerging workloads that require high memory bandwidth, Processing-in-Memory (PIM) has gained significant attention and led several industrial PIM products to be introduced which are integrated with conventional computing systems. This letter characterizes the data transfer overheads between conventional DRAM address space and PIM address space within a PIM-integrated system using the commercialized PIM device made by UPMEM. Our findings highlight the need for optimization in PIM-integrated systems to address these overheads, offering critical insights for future PIM technologies.

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商业 PIM 系统中的数据传输瓶颈分析：UPMEM-PIM 研究

由于新出现的工作负载需要较高的内存带宽，内存处理（PIM）备受关注，并推出了几款与传统计算系统集成的工业 PIM 产品。本文利用 UPMEM 生产的商业化 PIM 设备，描述了 PIM 集成系统中传统 DRAM 地址空间和 PIM 地址空间之间的数据传输开销。我们的研究结果凸显了在 PIM 集成系统中针对这些开销进行优化的必要性，为未来的 PIM 技术提供了重要的启示。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.