Architecting Compatible PIM Protocol for CPU-PIM Collaboration

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2024-07-24 DOI:10.1109/LCA.2024.3432936

Seunghyuk Yu;Hyeonu Kim;Kyoungho Jeun;Sunyoung Hwang;Eojin Lee

引用次数: 0

Abstract

Processing in Memory (PIM) technology is gaining traction with the introduction of several prototype products. However, the interfaces of existing PIM devices hinder CPU performance excessively by delaying normal memory requests for long periods during PIM operations. In this paper, we propose a new PIM command and protocol designed for compatibility across various PIM devices and host processors, focusing on DRAM standards with limited command space. Our proposed command, PIM-ACT, activates multiple banks simultaneously with assigning the specific PIM operation. It closely follows the functionality of the ACT command for straightforward control by the memory controller. We also explore memory scheduling policies that balance the latency of conventional memory requests with the throughput of PIM workloads. Our evaluation demonstrates the effectiveness of our approach in optimizing both PIM and conventional workload performance.

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为 CPU-PIM 协作构建兼容的 PIM 协议

随着一些原型产品的推出，内存处理（PIM）技术正日益受到重视。然而，现有 PIM 设备的接口会在 PIM 操作期间长时间延迟正常的内存请求，从而严重影响 CPU 性能。在本文中，我们提出了一种新的 PIM 命令和协议，旨在兼容各种 PIM 设备和主机处理器，重点关注命令空间有限的 DRAM 标准。我们提出的 PIM-ACT 命令可同时激活多个存储体，并分配特定的 PIM 操作。它与 ACT 命令的功能密切相关，可由内存控制器直接控制。我们还探索了内存调度策略，以平衡传统内存请求的延迟和 PIM 工作负载的吞吐量。我们的评估证明了我们的方法在优化 PIM 和传统工作负载性能方面的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.