IEEE Computer Architecture Letters最新文献_第7页

JBOC: Just a Bunch of CXL-Enabled SSDs for Resource-Efficient LLM Checkpointing JBOC：只是一堆支持xml的ssd，用于资源高效的LLM检查点

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-20 DOI: 10.1109/LCA.2026.3676331

Hakbeom Jang;Younghoon Min;Dongha Yoon;Hane Yie;Hoshik Kim;Jongryool Kim

{"title":"JBOC: Just a Bunch of CXL-Enabled SSDs for Resource-Efficient LLM Checkpointing","authors":"Hakbeom Jang;Younghoon Min;Dongha Yoon;Hane Yie;Hoshik Kim;Jongryool Kim","doi":"10.1109/LCA.2026.3676331","DOIUrl":"https://doi.org/10.1109/LCA.2026.3676331","url":null,"abstract":"The rapid growth of Large Language Models (LLMs) has pushed training systems to rely on memory sharding and offloading, introducing substantial data movement overhead. This is further exacerbated by frequent checkpointing, where training states must traverse multiple software and hardware layers. Such a process creates a critical performance bottleneck, as traditional host-centric hierarchies struggle to handle the massive data movement required for high-frequency, fault-tolerant checkpointing. In this paper, we introduce JBOC, an in-device processing architecture leveraging CXL-enabled SSDs that fuses optimizer updates and checkpointing into a single, unified operation. By offloading massive footprint optimizer updates and executing these fused tasks directly within internal computational units, JBOC achieves highly efficient checkpointing as persistence is handled during the update pipeline. This offloaded approach allows training states to remain within device-side resources, bypassing the host-side resource hierarchy and effectively isolating the host from heavy storage traffic. We validate JBOC on commercial CXL platforms from Marvell and SK Hynix. Our evaluation achieves up to a <inline-formula><tex-math>$4.40,times$</tex-math></inline-formula> speedup under per-iteration checkpointing. Compared to ZeRO-Offload, JBOC delivers comparable throughput while checkpointing <inline-formula><tex-math>$10,times$</tex-math></inline-formula> more frequently. Furthermore, JBOC outperforms both ZeRO-Offload and ZeRO-Infinity in memory-constrained scenarios, demonstrating its robustness when host resources are limited.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"182-185"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Wafer-Scale GPU Memory Pool With In-Package Optics for Enhanced Capacity and Bandwidth 晶圆级GPU内存池与封装光学增强容量和带宽

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-22 DOI: 10.1109/LCA.2026.3696219

Khakim Akhunov;Aakash Patel;Robert Kleijnen;Julien Ryckaert;James Myers;Dwaipayan Biswas

引用次数: 0

MMC: Metadata Migration for Efficient Memory Management in CXL DRAM Systems CXL DRAM系统中高效内存管理的元数据迁移

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-04-24 DOI: 10.1109/LCA.2026.3687345

Dusol Lee;Taehyung Lee;Hanseon Lee;Nam Sung Kim;Jihong Kim

引用次数: 0

Smart Prediction of I/O Accesses in Enterprise Workloads to Accelerate Data Serving During Array Reconstruction 对企业工作负载的I/O访问进行智能预测，加速阵列重构过程中的数据服务

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-19 DOI: 10.1109/LCA.2026.3669450

Mohammad M. Gharaguzlo;Mohammadamin Ajdari;Hossein Asadi

{"title":"Smart Prediction of I/O Accesses in Enterprise Workloads to Accelerate Data Serving During Array Reconstruction","authors":"Mohammad M. Gharaguzlo;Mohammadamin Ajdari;Hossein Asadi","doi":"10.1109/LCA.2026.3669450","DOIUrl":"https://doi.org/10.1109/LCA.2026.3669450","url":null,"abstract":"Storage systems in mission-critical environments require steady high performance all the time. When a <italic>Solid-State Drive (SSD) fails within a disk array, the array reconstruction starts and therefore, serving the application I/O request rate slows down. As our <italic>first contribution, we reveal that SSD arrays suffer from up to 3.3× drop of <italic>I/O per Second (IOPS) of serving enterprise workloads during SSD array reconstruction. To mitigate the array reconstruction problem, existing studies modify RAID algorithms, which make them inapplicable to many deployed SAN storage systems. Others propose predicting hot workload accesses during array reconstruction, and serving those addresses from a faster device. Unfortunately, we observe that such approaches mainly focus on short history, or have improper weight assignment for long history tracking, thus suffer from incomplete access predictions, and low acceleration opportunities. As the <italic>second contribution, we propose a novel I/O history pattern analysis, which applies proper weights for short- and long-term to maximize detection of repeated workload accesses during array reconstruction. We implement our proposed method and evaluate its effectiveness on a real system using enterprise workload I/O traces. Our proposed method predicts 80% more hot requests compared to state-of-art, which enables <italic>27% higher average IOPS during array reconstruction.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"101-104"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147557649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dicemite: Scaling Shared-Memory Isolation for Highly Consolidated FaaS Workers Dicemite：为高度整合的FaaS工作器扩展共享内存隔离

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-04-28 DOI: 10.1109/LCA.2026.3688492

Seonggyu Han;Jongmin Shin;Daehoon Kim

引用次数: 0

FeatureBleed: Inferring Private Enriched Attributes From Sparsity-Optimized AI Accelerators 从稀疏优化的AI加速器推断私有丰富属性

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-02-20 DOI: 10.1109/LCA.2026.3666823

Darsh Asher;Farshad Dizani;Joshua Kalyanapu;Rosario Cammarota;Aydin Aysu;Samira Mirbagher Ajorpaz

{"title":"FeatureBleed: Inferring Private Enriched Attributes From Sparsity-Optimized AI Accelerators","authors":"Darsh Asher;Farshad Dizani;Joshua Kalyanapu;Rosario Cammarota;Aydin Aysu;Samira Mirbagher Ajorpaz","doi":"10.1109/LCA.2026.3666823","DOIUrl":"https://doi.org/10.1109/LCA.2026.3666823","url":null,"abstract":"Backend enrichment deployed in sensitive domains such as product recommendation pipelines, healthcare, and finance, where models are trained on confidential data and retrieve private features whose values influence inference behavior while remaining hidden from the API caller. This paper presents the first <italic>hardware-level backend retrieval data-stealing attack, showing that accelerator optimizations designed for performance can directly undermine data confidentiality and bypass state-of-the-art privacy defenses. Our attack, <sc>FeatureBleed, exploits <italic>zero-skipping in AI accelerators to infer private backend-retrieved features solely through end-to-end timing, without relying on power analysis, DVFS manipulation, or shared-cache side channels. We evaluate <sc>FeatureBleed on three datasets spanning medical and non-medical domains—Texas-100X (clinical records), OrganAMNIST (medical imaging), and Census-19 (socioeconomic data). We further evaluate <sc>FeatureBleed across three hardware backends (Intel AVX, Intel AMX, and NVIDIA A100) and three model architectures (DNNs, CNNs, and hybrid CNN–MLP pipelines), demonstrating that the leakage generalizes across CPU and GPU accelerators, data modalities, and application domains, with an adversarial advantage of up to <bold>98.87 pp. Finally, we identify the root cause of the leakage as sparsity-driven zero-skipping in modern hardware. We quantify the privacy–performance–power trade-off: disabling zero-skipping increases Intel AMX’s per-operation energy by up to <bold>25% and incurs <bold>100% performance overhead. We propose a padding-based defense that masks timing leakage by equalizing responses to the worst-case execution time, achieving protection with only <bold>7.24% average performance overhead and no additional power cost is now widely.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"77-80"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148478829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reducing LLM Inference Memory Bandwidth via Frequent Exponent Value Encoding 通过频繁指数值编码减少LLM推理存储器带宽

IF 2 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-06 DOI: 10.1109/LCA.2026.3671166

Maxwell Michalec;Swamit Tannu;Gurindar Sohi

引用次数: 0

An Operand Divergence-Aware All-Bank PIM Architecture for Sparse Attention 面向稀疏关注的操作数发散感知全银行PIM体系结构

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-04-15 DOI: 10.1109/LCA.2026.3684216

Soojin Hwang;Sanghyeon Lee;Juhyun Lee;Jaehyuk Huh

引用次数: 0

Enabling Computation and Communication Overlap in PIMs for On-Device LLM Inference 基于设备上LLM推理的PIMs计算和通信重叠实现