章鱼:周期精确的高速缓存系统模拟器

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Mohamed Hossam;Salah Hessien;Mohamed Hassan
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引用次数: 0

摘要

本文介绍了具有灵活互连模型的开源周期精确高速缓存系统模拟器 Octopus1。Octopus 可细致模拟各种高速缓存系统和互连组件,包括控制器、数据阵列、一致性协议和仲裁器。周期精确性使 Octopus 能够精确模拟目标系统的行为,同时逐周期监控每个内存请求。Octopus 的设计方法有别于现有的高速缓冲存储器模拟器,因为它不强制执行固定的内存系统架构,而是灵活配置组件连接和参数,从而能够模拟各种内存架构。此外,该模拟器还提供了独立和全系统模拟两种双重操作模式,从而实现了两全其美的效果:快速模拟和高精度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Octopus: A Cycle-Accurate Cache System Simulator
This paper introduces Octopus 1 , an open-source cycle-accurate cache system simulator with flexible interconnect models. Octopus meticulously simulates various cache system and interconnect components, including controllers, data arrays, coherence protocols, and arbiters. Being cycle-accurate enables Octopus to precisely model the behavior of target systems, while monitoring every memory request cycle by cycle. The design approach of Octopus distinguishes it from existing cache memory simulators, as it does not enforce a fixed memory system architecture but instead offers flexibility in configuring component connections and parameters, enabling simulation of diverse memory architectures. Moreover, the simulator provides two dual modes of operation, standalone and full-system simulation, which attains the best of both worlds benefits: fast simulations and high accuracy.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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