Characterization and Analysis of Text-to-Image Diffusion Models

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2024-09-26 DOI:10.1109/LCA.2024.3466118

Eunyeong Cho;Jehyeon Bang;Minsoo Rhu

引用次数: 0

Abstract

Diffusion models have rapidly emerged as a prominent AI model for image generation. Despite its importance, however, little have been understood within the computer architecture community regarding this emerging AI algorithm. We conduct a workload characterization on the inference process of diffusion models using Stable Diffusion. Our characterization uncovers several critical performance bottlenecks of diffusion models, the computational overhead of which gets aggravated as image size increases. We also discuss several performance optimization opportunities that leverage approximation and sparsity, which help alleviate diffusion model's computational complexity. These findings highlight the need for domain-specific hardware that reaps out the benefits of our proposal, paving the way for accelerated image generation.

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文本到图像扩散模型的特征和分析

扩散模型已迅速成为图像生成方面的一个重要人工智能模型。然而，尽管扩散模型非常重要，计算机体系结构界对这种新兴的人工智能算法却知之甚少。我们利用稳定扩散技术对扩散模型的推理过程进行了工作量鉴定。我们的分析发现了扩散模型的几个关键性能瓶颈，其计算开销随着图像大小的增加而加剧。我们还讨论了利用近似性和稀疏性进行性能优化的几个机会，这有助于减轻扩散模型的计算复杂性。这些发现凸显了对特定领域硬件的需求，这些硬件可以充分利用我们建议的优势，为加速图像生成铺平道路。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.