IEEE Computer Architecture Letters最新文献_第5页

Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator 在商用内存计算加速器上支持虚拟矢量指令集

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-12-11 DOI: 10.1109/LCA.2023.3341389

Courtney Golden;Dan Ilan;Caroline Huang;Niansong Zhang;Zhiru Zhang;Christopher Batten

引用次数: 0

Exploiting Intrinsic Redundancies in Dynamic Graph Neural Networks for Processing Efficiency 利用动态图神经网络的内在冗余提高处理效率

IF 1.4 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-12-07 DOI: 10.1109/LCA.2023.3340504

Deniz Gurevin;Caiwen Ding;Omer Khan

{"title":"Exploiting Intrinsic Redundancies in Dynamic Graph Neural Networks for Processing Efficiency","authors":"Deniz Gurevin;Caiwen Ding;Omer Khan","doi":"10.1109/LCA.2023.3340504","DOIUrl":"10.1109/LCA.2023.3340504","url":null,"abstract":"Modern dynamical systems are rapidly incorporating artificial intelligence to improve the efficiency and quality of complex predictive analytics. To efficiently operate on increasingly large datasets and intrinsically dynamic non-euclidean data structures, the computing community has turned to Graph Neural Networks (GNNs). We make a key observation that existing GNN processing frameworks do not efficiently handle the intrinsic dynamics in modern GNNs. The dynamic processing of GNN operates on the complete static graph at each time step, leading to repetitive redundant computations that introduce tremendous under-utilization of system resources. We propose a novel dynamic graph neural network (DGNN) processing framework that captures the dynamically evolving dataflow of the GNN semantics, i.e., graph embeddings and sparse connections between graph nodes. The framework identifies intrinsic redundancies in node-connections and captures representative node-sparse graph information that is readily ingested for processing by the system. Our evaluation on an NVIDIA GPU shows up to 3.5× speedup over the baseline setup that processes all nodes at each time step.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2023-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142183932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing the Reach and Reliability of Quantum Annealers by Pruning Longer Chains 通过修剪长链提高量子退火器的覆盖范围和可靠性

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-12-06 DOI: 10.1109/LCA.2023.3340030

Ramin Ayanzadeh;Moinuddin Qureshi

{"title":"Enhancing the Reach and Reliability of Quantum Annealers by Pruning Longer Chains","authors":"Ramin Ayanzadeh;Moinuddin Qureshi","doi":"10.1109/LCA.2023.3340030","DOIUrl":"https://doi.org/10.1109/LCA.2023.3340030","url":null,"abstract":"Analog Quantum Computers (QCs), such as D-Wave's \u0000<italic>Quantum Annealers\u0000 (\u0000<italic>QAs\u0000) and QuEra's neutral atom platform, rival their digital counterparts in computing power. Existing QAs boast over 5,700 qubits, but their single-instruction operation model prevents using SWAP operations for making physically distant qubits adjacent. Instead, QAs use an \u0000<italic>embedding\u0000 process to chain multiple \u0000<italic>physical qubits\u0000 together, representing a \u0000<italic>program qubit\u0000 with higher connectivity and reducing effective QA capacity by up to 33x. We observe that, post-embedding, nearly 25% of physical qubits remain unused, becoming trapped between chains. Additionally, we observe a “Power-Law” distribution in the chain lengths, where a few \u0000<italic>dominant chains\u0000 possess significantly more qubits, thereby exerting a considerably more significant impact on both qubit utilization and isolation. Leveraging these insights, we propose \u0000<italic>Skipper\u0000, a software technique designed to enhance the capacity and fidelity of QAs by skipping dominant chains and substituting their program qubit with two measurement outcomes. Using a 5761-qubit QA, we observed that by skipping up to eleven chains, the capacity increased by up to 59% (avg 28%), and the error decreased by up to 44% (avg 33%).","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139976212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Tulip: Turn-Free Low-Power Network-on-Chip 郁金香免转低功耗片上网络

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-12-05 DOI: 10.1109/LCA.2023.3339646

Atiyeh Gheibi-Fetrat;Negar Akbarzadeh;Shaahin Hessabi;Hamid Sarbazi-Azad

{"title":"Tulip: Turn-Free Low-Power Network-on-Chip","authors":"Atiyeh Gheibi-Fetrat;Negar Akbarzadeh;Shaahin Hessabi;Hamid Sarbazi-Azad","doi":"10.1109/LCA.2023.3339646","DOIUrl":"https://doi.org/10.1109/LCA.2023.3339646","url":null,"abstract":"The semiconductor industry has seen significant technological advancements, leading to an increase in the number of processing cores in a system-on-chip (SoC). To facilitate communication among the numerous on-chip cores, a network-on-chip (NoC) is employed. One of the main challenges of designing NoCs is power management since the NoC consumes a significant portion of the total power of the SoC. Among the power-intensive components of the NoC, routers stand out. We observe that some power-intensive components of routers, responsible for implementing turn in the mesh topology, are underutilized compared to others. Therefore, we propose Tulip, a turn-free low-power network-in-chip, that avoids within-router turns by removing the corresponding components from the router structure. On a turn (e.g., at the end of the current dimension), Tulip forces the packet to be ejected and then reinjects it to the next dimension channel (i.e., the beginning of the path along the next dimension). Due to its deadlock-free nature, Tulip's scheme may be used orthogonally with any deterministic, partially-adaptive, and fully-adaptive routing algorithms, and can easily be extended for any n-dimensional mesh topology. Our analysis reveals that Tulip can reduce the static power and area by 24%−50% and 25%-55%, respectively, for 2D-5D mesh routers.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139060173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems 用于个性化推荐系统的 FPGA 加速数据预处理

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-11-28 DOI: 10.1109/LCA.2023.3336841

Hyeseong Kim;Yunjae Lee;Minsoo Rhu

引用次数: 0

Redundant Array of Independent Memory Devices 独立内存设备冗余阵列

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-11-20 DOI: 10.1109/LCA.2023.3334989

Peiyun Wu;Trung Le;Zhichun Zhu;Zhao Zhang

引用次数: 0

Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator Ramulator 2.0：现代、模块化、可扩展的 DRAM 仿真器

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-11-17 DOI: 10.1109/LCA.2023.3333759

Haocong Luo;Yahya Can Tuğrul;F. Nisa Bostancı;Ataberk Olgun;A. Giray Yağlıkçı;Onur Mutlu

{"title":"Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator","authors":"Haocong Luo;Yahya Can Tuğrul;F. Nisa Bostancı;Ataberk Olgun;A. Giray Yağlıkçı;Onur Mutlu","doi":"10.1109/LCA.2023.3333759","DOIUrl":"https://doi.org/10.1109/LCA.2023.3333759","url":null,"abstract":"We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and DRAM to meet the increasing research effort in improving the performance, security, and reliability of memory systems. Ramulator 2.0 abstracts and models key components in a DRAM-based memory system and their interactions into shared \u0000<italic>interfaces\u0000 and independent \u0000<italic>implementations\u0000. Doing so enables easy modification and extension of the modeled functions of the memory controller and DRAM in Ramulator 2.0. The DRAM specification syntax of Ramulator 2.0 is concise and human-readable, facilitating easy modifications and extensions. Ramulator 2.0 implements a library of reusable templated lambda functions to model the functionalities of DRAM commands to simplify the implementation of new DRAM standards, including DDR5, LPDDR5, HBM3, and GDDR6. We showcase Ramulator 2.0's modularity and extensibility by implementing and evaluating a wide variety of RowHammer mitigation techniques that require \u0000<italic>different\u0000 memory controller design changes. These techniques are added modularly as separate implementations \u0000<italic>without\u0000 changing \u0000<italic>any\u0000 code in the baseline memory controller implementation. Ramulator 2.0 is rigorously validated and maintains a fast simulation speed compared to existing cycle-accurate DRAM simulators.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140822019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Towards an Accelerator for Differential and Algebraic Equations Useful to Scientists 开发对科学家有用的微分方程和代数方程加速器

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-11-13 DOI: 10.1109/LCA.2023.3332318

Jonathan Garcia-Mallen;Shuohao Ping;Alex Miralles-Cordal;Ian Martin;Mukund Ramakrishnan;Yipeng Huang

引用次数: 0

gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation gem5-accel：用于加速器架构验证的预 RTL 仿真工具链

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-11-01 DOI: 10.1109/LCA.2023.3329443

João Vieira;Nuno Roma;Gabriel Falcao;Pedro Tomás

引用次数: 0

Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations 减少基于计数器的行锤缓解措施的硅面积开销

IF 2.3 3区计算机科学

IEEE Computer Architecture Letters Pub Date : 2023-10-31 DOI: 10.1109/LCA.2023.3328824

Loïc France;Florent Bruguier;David Novo;Maria Mushtaq;Pascal Benoit

引用次数: 0