Accelerating Vector Permutation Instruction Execution via Controllable Bitonic Network

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2025-03-05 DOI:10.1109/LCA.2025.3548527

Shabirahmed Badashasab Jigalur;Daniel Jiménez Mazure;Teresa Cervero Garcia;Yen-Cheng Kuan

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引用次数: 0

Abstract

High-performance computing applications rely heavily on vector instructions to accelerate data processing. In this letter, we propose a controllable bitonic network (CBN) and use it as a lane interconnect to efficiently rearrange data across vector lanes of a vector processing unit to accelerate the execution of vector permutation instructions (VPIs). Our work focuses on the RISC-V vector instruction set because of its configurable vector length support. Through simulations with vector-permutation-intensive applications of a RISC-V vector benchmark suite (RiVEC), the proposed approach with an eight-lane 64-bit CBN demonstrates an average speedup of ≥6× regarding the VPI execution time over a conventional ring-network-based approach. In addition, to verify our approach on hardware, we implemented a processor system with an eight-lane 16-bit CBN on an AMD A7-100T FPGA operating at 20 MHz, demonstrating single-cycle execution of the RISC-V vr.gather and vr.scatter instructions.

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通过可控双元网络加速矢量置换指令的执行

高性能计算应用程序严重依赖矢量指令来加速数据处理。在本文中，我们提出了一种可控双元网络（CBN），并将其用作通道互连，以有效地重新排列矢量处理单元的矢量通道中的数据，以加速矢量置换指令（vpi）的执行。我们的工作重点是RISC-V矢量指令集，因为它支持可配置的矢量长度。通过对RISC-V矢量基准套件（RiVEC）的矢量置换密集型应用的模拟，所提出的八车道64位CBN方法在VPI执行时间方面的平均加速速度比传统的基于环网络的方法提高了≥6倍。此外，为了在硬件上验证我们的方法，我们在AMD A7-100T FPGA上实现了一个具有8通道16位CBN的处理器系统，工作频率为20 MHz，演示了RISC-V vr的单周期执行。集合起来。分散指令。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.