Cycle-Oriented Dynamic Approximation: Architectural Framework to Meet Performance Requirements

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2024-08-06 DOI:10.1109/LCA.2024.3439318

Yuya Degawa;Shota Suzuki;Junichiro Kadomoto;Hidetsugu Irie;Shuichi Sakai

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引用次数: 0

Abstract

Approximate computing achieves shorter execution times and reduced energy consumption in areas where precise computation written in a program is not essential to meet a goal. When applying the approximations, it is vital to satisfy the required quality-of-service (QoS) (execution time) and quality-of-results (QoR) (output accuracy). Existing methods have difficulty in maintaining a constant QoS or impose a burden on programmers. In this study, we propose the Cycle-oriented Dynamic Approximation (CODAX) algorithms and processor architecture that minimize the burden on the programmer and maintain the execution time close to the required QoS while providing the user with an option to satisfy their QoR requirement. CODAX operates based on a threshold that indicates the maximum number of cycles available for one loop iteration. The threshold automatically increases or decreases at runtime to bring the total number of elapsed cycles close to the required QoS. Furthermore, CODAX allows the user to change the threshold to indirectly guarantee the required QoR. Our simulation revealed that CODAX brought the actual number of executed cycles close to the expected number for four workloads.

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面向周期的动态逼近：满足性能要求的架构框架

近似计算可以缩短执行时间，降低能耗，在这些领域中，程序中的精确计算对于实现目标并非必不可少。在应用近似计算时，满足所需的服务质量（QoS）（执行时间）和结果质量（QoR）（输出精确度）至关重要。现有的方法难以保持稳定的 QoS，或给程序员带来负担。在本研究中，我们提出了面向循环的动态逼近 (CODAX) 算法和处理器架构，可最大限度地减轻程序员的负担，并将执行时间保持在所需的 QoS 附近，同时为用户提供满足 QoR 要求的选择。CODAX 基于一个阈值运行，该阈值表示一个循环迭代可用的最大周期数。该阈值会在运行时自动增加或减少，以使循环总次数接近所需的 QoS。此外，CODAX 还允许用户更改阈值，以间接保证所需的 QoR。我们的模拟显示，CODAX 使四种工作负载的实际执行周期数接近预期数。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.