Journal of Electronic Testing最新文献_第2页

Formal Verification of Universal Numbers using Theorem Proving 利用定理证明对万国数进行形式验证

Journal of Electronic Testing Pub Date : 2024-06-28 DOI: 10.1007/s10836-024-06123-9

Adnan Rashid, Ayesha Gauhar, Osman Hasan, Sa’ed Abed, Imtiaz Ahmad

{"title":"Formal Verification of Universal Numbers using Theorem Proving","authors":"Adnan Rashid, Ayesha Gauhar, Osman Hasan, Sa’ed Abed, Imtiaz Ahmad","doi":"10.1007/s10836-024-06123-9","DOIUrl":"https://doi.org/10.1007/s10836-024-06123-9","url":null,"abstract":"A universal number (Unum) is a number representation format that can reduce the memory contention issues in multicore processors and parallel computing systems by optimizing the bit storage in the arithmetic operations. Given the safety-critical nature of applications of Unum format, there is a dire need to rigorously assess the correctness of the Unum based arithmetic operations. Unums are of three types, namely, Unum-I, Unum-II and Unum-III (commonly known as Posits). In this paper, we provide a higher-order-logic formalization of Unum-III (posits). In particular, we formally model a posit format (binary encoding of a posit), which is comprised of the sign, exponent, regime and fraction bits, using the HOL Light theorem prover. In order to prove the correctness of a posit format, we formally verify various properties regarding conversions of a real number to a posit and a posit to a real number and the scaling factors of the regime, exponent and fraction bits of a posit using HOL Light.","PeriodicalId":501485,"journal":{"name":"Journal of Electronic Testing","volume":"61 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141501237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm 使用遗传算法利用经济有效的测试向量检测硬件木马

Journal of Electronic Testing Pub Date : 2024-06-25 DOI: 10.1007/s10836-024-06122-w

Sandip Chakraborty, Archisman Ghosh, Anindan Mondal, Bibhash Sen

{"title":"Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm","authors":"Sandip Chakraborty, Archisman Ghosh, Anindan Mondal, Bibhash Sen","doi":"10.1007/s10836-024-06122-w","DOIUrl":"https://doi.org/10.1007/s10836-024-06122-w","url":null,"abstract":"Hardware Trojans (HT) are tiny circuits designed to exploit electronic devices, posing risks such as device malfunction or leakage of sensitive information. The adversary aims to implant these HTs specifically targeting nets with minimal signal transition (rare gates) within a circuit, evading detection during functional tests. Some Trojan variants are activated by adversaries under specific periodic conditions. Logic testing, a well-established method for test generation in HT detection, faces challenges due to the impractical scale of the search space, whereas Genetic Algorithms (GA) excel in efficiently navigating extensive solution spaces. This paper presents a GA-based technique that integrates information on effective inputs, along with an adequate fitness function defined based on combinational controllability and structural features, for detecting conditionally triggered ultrasmall HTs. Upon assessing the ITC 99 and ISCAS 85 and 89 benchmarks, we note significant enhancements in trigger coverage and reduced run-time requirements in comparison to state-of-the-art methods like MERO and TRIAGE.","PeriodicalId":501485,"journal":{"name":"Journal of Electronic Testing","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141501238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Framework For Optimal Test Case Generation and Prioritization Using Ent-LSOA And IMTRNN Techniques 使用 Ent-LSOA 和 IMTRNN 技术优化测试用例生成和优先级排序的新框架

Journal of Electronic Testing Pub Date : 2024-06-20 DOI: 10.1007/s10836-024-06121-x

A. Tamizharasi, P. Ezhumalai

{"title":"A Novel Framework For Optimal Test Case Generation and Prioritization Using Ent-LSOA And IMTRNN Techniques","authors":"A. Tamizharasi, P. Ezhumalai","doi":"10.1007/s10836-024-06121-x","DOIUrl":"https://doi.org/10.1007/s10836-024-06121-x","url":null,"abstract":"Test Case Generation (TCG) generates various types of tests, including functional tests, performance tests, security tests, and reliability tests to ensure software quality, while Test Case Prioritization (TCP) prioritizes the generated tests. However, the previous studies had challenges, including resource constraints, detecting crucial requirements, and automating the Test Case (TC) process efficiently. Additionally, the process is costlier and takes a maximum time duration that affects the effective performance. Therefore, an effective framework is proposed to overcome such issues by optimizing TCG and TCP processes effectively. The proposed work starts with the generation of a Unified Modeling Language (UML) diagram from historical project source code, which is then converted into a Comma-Separated Value (CSV) format. Then, the feature extraction is performed on this CSV file, followed by optimal TCG using the Entropy-based Locust Swarm Optimization Algorithm (Ent-LSOA). Additionally, factors are extracted and reduced from the historical project source code using Pearson Correlation Coefficient-Generalized Discriminant Analysis (PCC-GDA). Finally, the optimal TCs and selected factors are prioritized with the highest accuracy and recall of 96.89% and 96.92%, respectively using an Interpolated Multiple Time scale Recurrent Neural Network (IMTRNN). Thus, the proposed work outperformed the existing techniques by providing an efficient solution for TCG and TCP in software testing.","PeriodicalId":501485,"journal":{"name":"Journal of Electronic Testing","volume":"82 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141501239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach 基于图划分和概率二项式方法的组合电路故障率分析

Journal of Electronic Testing Pub Date : 2024-05-28 DOI: 10.1007/s10836-024-06119-5

Esther Goudet, Fabio Sureau, Paul Breuil, Luis Peña Treviño, Lirida Naviner, Jean-Marc Daveau, Philippe Roche

{"title":"Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach","authors":"Esther Goudet, Fabio Sureau, Paul Breuil, Luis Peña Treviño, Lirida Naviner, Jean-Marc Daveau, Philippe Roche","doi":"10.1007/s10836-024-06119-5","DOIUrl":"https://doi.org/10.1007/s10836-024-06119-5","url":null,"abstract":"This paper studies the fault propagation and the correctness rate calculation of combinatorial circuits. We rely on circuit partitioning and on a probabilistic approach close to a binomial distribution, assuming some simultaneous faults have a certain probability to occur in the circuit’s gates. We extend the results of our Clusterized Probabilistic Binomial Reliability model (CPBR), in which we obtained the results for several combinatorial multiplier designs, as seen in our previous publication. We now target non-arithmetic combinatorial netlists and, among them, a few circuits with flip-flop instances. We use the graph representation of the combinatorial netlists and we generalize our approach with a generic algorithm for CPBR. To develop this algorithm, we use some existing work on multilevel acyclic hypergraph partitioning, that we adapt to acyclic directed graphs. Furthermore, we address the problem of calculating correctness rates of circuits in cases where sequential flip-flops induce cycles in the graph. Our experiments show that our approach is capable of analysing the error and the correctness rates of significant non-arithmetic circuits, with an automatized and generic tool.","PeriodicalId":501485,"journal":{"name":"Journal of Electronic Testing","volume":"38 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141170349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Phase Noise Analysis Performance Improvement, Testing and Stabilization of Microwave Frequency Source 相位噪声分析微波频率源的性能改进、测试和稳定

Journal of Electronic Testing Pub Date : 2024-05-07 DOI: 10.1007/s10836-024-06118-6

Vipin Kumar, Jayanta Ghosh

{"title":"Phase Noise Analysis Performance Improvement, Testing and Stabilization of Microwave Frequency Source","authors":"Vipin Kumar, Jayanta Ghosh","doi":"10.1007/s10836-024-06118-6","DOIUrl":"https://doi.org/10.1007/s10836-024-06118-6","url":null,"abstract":"The present article proposes a novel method to reduce phase noise in a PLL based X-Band source consisting of oscillating and non-oscillating components for the use in Pulse Doppler radar. It also provides phase noise performance stabilization under random vibration. The method consists of improved electrical design and PCB layout, noise filtering technique and passive isolation scheme to suppress vibration-induced noise. Acceleration sensitivity is an important requirement for radars and sensors mounted in unmanned aerial vehicles, aircrafts, missiles and other dynamic platforms. These systems provide superior performance when subjected to severe environmental condition. However, mechanical vibration and acceleration can introduce physical deformation that thereby degrades the frequency source generated signal phase noise. It effects the complete radar system that depends on frequency source performance. The development and testing of a stable X-Band source at 10.64 GHz using indirect method has been carried out which proved that the phase noise is stable both in steady state and under random vibration of 7g magnitude. The study of critical design aspects of test fixture, test object mounting arrangement, investigation on vibration response and performance stabilization along with description of test setup and measurement procedure has been reported. An improvement of around 35-40 dB in phase noise is achieved at close-in offset frequencies. Few challenges and suggestions for the accurate measurement of random vibration testing for frequency sources have also been mentioned.","PeriodicalId":501485,"journal":{"name":"Journal of Electronic Testing","volume":"33 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140936144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application 用于低功率锁相环应用的基于设计的抗辐射压控振荡器

Journal of Electronic Testing Pub Date : 2024-04-17 DOI: 10.1007/s10836-024-06113-x

Rachana Ahirwar, Manisha Pattanaik, Pankaj Srivastava

{"title":"Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application","authors":"Rachana Ahirwar, Manisha Pattanaik, Pankaj Srivastava","doi":"10.1007/s10836-024-06113-x","DOIUrl":"https://doi.org/10.1007/s10836-024-06113-x","url":null,"abstract":"A radiation-hardened-by-design (RHBD) current-starved-ring voltage-controlled oscillator (CSR-VCO) design is proposed based on the separation of gate input technique to mitigate single event effects (SEEs) for phase-locked loop (PLL) implementation. A double-exponential (DE) current model is used to analyze the effect of single event transient (SET) at the output of the proposed RHBD CSR-VCO. The proposed RHBD CSR-VCO is implemented in United Microelectronics Corporation (UMC) 65 nm CMOS technology and a 71.6% improvement is achieved in phase displacement as compared to conventional VCO. The oscillation frequency of 1.75 GHz is obtained for the proposed RHBD CSR-VCO with a tuning range from 0.40 GHz to 2.23 GHz and power dissipation of 1.368 mW. The proposed RHBD CSR-VCO is protected against radiation with deposited charges up to 1050 fC and achieved a higher figure-of-merit (FOM) when compared to the recently reported VCOs and PLLs. This shows that even in a radiation-prone environment, the RHBD PLL can achieve excellent performance and be employed successfully in low-power, high-speed communication applications.","PeriodicalId":501485,"journal":{"name":"Journal of Electronic Testing","volume":"57 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140609279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis 用于模拟电路故障诊断的端到端互斥自动编码器方法

Journal of Electronic Testing Pub Date : 2024-04-16 DOI: 10.1007/s10836-023-06097-0

Yuling Shang, Songyi Wei, Chunquan Li, Xiaojing Ye, Lizhen Zeng, Wei Hu, Xiang He, Jinzhuo Zhou

引用次数: 0

A Survey and Recent Advances: Machine Intelligence in Electronic Testing 概览与最新进展：电子测试中的机器智能

Journal of Electronic Testing Pub Date : 2024-04-15 DOI: 10.1007/s10836-024-06117-7

Soham Roy, Spencer K. Millican, Vishwani D. Agrawal

引用次数: 0

Sahand: A Software Fault-Prediction Method Using Autoencoder Neural Network and K-Means Algorithm Sahand：使用自动编码器神经网络和 K-Means 算法的软件故障预测方法

Journal of Electronic Testing Pub Date : 2024-04-12 DOI: 10.1007/s10836-024-06116-8

Bahman Arasteh, Sahar Golshan, Shiva Shami, Farzad Kiani

{"title":"Sahand: A Software Fault-Prediction Method Using Autoencoder Neural Network and K-Means Algorithm","authors":"Bahman Arasteh, Sahar Golshan, Shiva Shami, Farzad Kiani","doi":"10.1007/s10836-024-06116-8","DOIUrl":"https://doi.org/10.1007/s10836-024-06116-8","url":null,"abstract":"Software is playing a growing role in many safety-critical applications, and software systems dependability is a major concern. Predicting faulty modules of software before the testing phase is one method for enhancing software reliability. The ability to predict and identify the faulty modules of software can lower software testing costs. Machine learning algorithms can be used to solve software fault prediction problem. Identifying the faulty modules of software with the maximum accuracy, precision, and performance are the main objectives of this study. A hybrid method combining the autoencoder and the K-means algorithm is utilized in this paper to develop a software fault predictor. The autoencoder algorithm, as a preprocessor, is used to select the effective attributes of the training dataset and consequently to reduce its size. Using an autoencoder with the K-means clustering method results in lower clustering error and time. Tests conducted on the standard NASA PROMIS data sets demonstrate that by removing the inefficient elements from the training data set, the proposed fault predictor has increased accuracy (96%) and precision (93%). The recall criteria provided by the proposed method is about 87%. Also, reducing the time necessary to create the software fault predictor is the other merit of this study.","PeriodicalId":501485,"journal":{"name":"Journal of Electronic Testing","volume":"16 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140579483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission 单次事件效应和空间静电放电效应对 FPGA 信号传输的影响比较

Journal of Electronic Testing Pub Date : 2024-04-04 DOI: 10.1007/s10836-024-06114-w

Rongxing Cao, Yan Liu, Yulong Cai, Bo Mei, Lin Zhao, Jiayu Tian, Shuai Cui, He Lv, Xianghua Zeng, Yuxiong Xue

引用次数: 0