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2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)最新文献

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Design of Photonic Filter Using Metamaterial Based Defected Ternary Structure Under Normal Incidence 正入射下基于超材料的缺陷三元结构光子滤波器的设计
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179900
Nabanita Pramanik, A. Deyasi, A. Sarkar
{"title":"Design of Photonic Filter Using Metamaterial Based Defected Ternary Structure Under Normal Incidence","authors":"Nabanita Pramanik, A. Deyasi, A. Sarkar","doi":"10.1109/VLSIDCS47293.2020.9179900","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179900","url":null,"abstract":"Ripple factor of ternary photonic bandpass filter is analytically computed around 1.55 μm under normal incidence of electromagnetic wave. Parallel nanorod is considered as the metamaterial for the simulation purpose with air gap, and transfer matrix technique is adopted for the investigation. Improved noise rejection characteristics are obtained compared to the published results for positive index materials. Different structural parameters are varied to observe the bandwidth as well as noise variation for optimized performance. The structure is taken as defected one, where the density of point defect is within the limit of fabrication, so that the simulated findings can be taken as realistic.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129752666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance Analysis of FinFETs with Strained-Si Fin on Strain-Relaxed Buffer 应变松弛缓冲器上应变硅片fet的性能分析
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179862
J. Jena, Tara Prasanna Dash, E. Mohaptra, S. Das, J. Nanda, C. K. Maiti
{"title":"Performance Analysis of FinFETs with Strained-Si Fin on Strain-Relaxed Buffer","authors":"J. Jena, Tara Prasanna Dash, E. Mohaptra, S. Das, J. Nanda, C. K. Maiti","doi":"10.1109/VLSIDCS47293.2020.9179862","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179862","url":null,"abstract":"The architecture of transistors has now switched from planar to the non-planar vertical structures. The 3-D geometry of such non-planar FinFET structures imposes new challenges especially on the computational level. Silicon channel N-type Fin shaped Field Effect Transistors (n-FinFETs) are being integrated with diamond-shaped embedded Si1−xGex fin Strain-Relaxed Buffer (SRB) to optimize the electrical performance. In this work, the stressor geometry (size and shape) effects on the device performance have been studied in detail. The mobility enhancement in n-FinFETs is observed due to process induced strain to increase the drive current. The higher percentage of Ge content shows better effect on device parameters SS, DIBL and VTH. The drain current is found to be improved for certain Ge content in the fin SRB.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122553193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic Generation Control in Restructured Power System with Capacitive Energy Storage and Communication Delay Based Cascaded Controller 基于电容储能和通信延迟级联控制器的重构电力系统自动发电控制
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179859
Prasun Sanki, M. Basu, P. Pal
{"title":"Automatic Generation Control in Restructured Power System with Capacitive Energy Storage and Communication Delay Based Cascaded Controller","authors":"Prasun Sanki, M. Basu, P. Pal","doi":"10.1109/VLSIDCS47293.2020.9179859","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179859","url":null,"abstract":"Present work demonstrates a novel approach adopting communication delay based PI-PD cascaded controller in automatic generation control (AGC) under deregulated power system scenario. Moth flame optimization (MFO) technique is adopted to tune controller gain parameters. In modern days, energy storage devices (ESDs) get enormous popularities in power system operation. In this regard, capacitive energy storage (CES) unit has been included in both the areas. Numerous case studies are performed considering various power exchange scenarios. Detailed mathematical formulations are presented in support of the simulated results. Time domain analyses also satisfy the performance of the suggested controller. All the scenarios are simulated to validate the robustness and sensitivity of the suggested controller using standard two area deregulated power system model under MATLAB / Simulink.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116105507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of Multiplexer Using Actin Quantum Cellular Automata 基于Actin量子元胞自动机的多路复用器设计
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179908
B. Das, Tapatosh Sadhu, D. De
{"title":"Design of Multiplexer Using Actin Quantum Cellular Automata","authors":"B. Das, Tapatosh Sadhu, D. De","doi":"10.1109/VLSIDCS47293.2020.9179908","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179908","url":null,"abstract":"Boolean logic functions is possible to realize using collisions in bio-molecular quantum automata systems. Actin is a thin muscle filament consisting of two protein chains that mainly contribute to animal nervous system and eukaryotic cellular structure. Actin quantum cellular automata is also capable of quantum computation with help of qubits, if superposition of states is employed in the input and conducting moves using rules that are applicable to each of the actin molecules. In the present work, design of multiplexers like 2x1 multiplexer using actin filaments are proposed. For the sake of simplicity, classical bit representation is used to realize logic gates like AND gate, NOT gate and OR gate with the quantum automata. Finally these gates are utilized to design the proposed multiplexer. By comparing the efficiency of methodologies used in designing the circuits, optimized design for the proposed multiplexer is suggested.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122867615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Computing Cut-off Wavelengths from Dispersion Characteristics for 2D Triangular Photonic Crystal Based Superlens 二维三角形光子晶体超透镜色散特性计算截止波长
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179946
Moumita Banerjee, P. Debnath, A. Deyasi
{"title":"Computing Cut-off Wavelengths from Dispersion Characteristics for 2D Triangular Photonic Crystal Based Superlens","authors":"Moumita Banerjee, P. Debnath, A. Deyasi","doi":"10.1109/VLSIDCS47293.2020.9179946","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179946","url":null,"abstract":"Cut-off wavelengths for first five bands are analytically evaluated from dispersion characteristics for photonic crystal based superlens. 2D PhC with triangular geometry is considered for simulation purpose where plane wave expansion method is utilized, and both TE and TM modes are taken into account for estimation. Different material compositions are applied with air to investigate the effect of varying dielectric constant cut-off wavelengths. Contour diagrams indicates that results exhibit that most of the wavelengths fall in UV ranges, which speaks in favor of designing superlens with high-K materials.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115217317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Three Input NAND Gate Using Semiconductor Optical Amplifier 采用半导体光放大器的三输入非与门
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179931
K. Mukherjee, A. Raja
{"title":"Three Input NAND Gate Using Semiconductor Optical Amplifier","authors":"K. Mukherjee, A. Raja","doi":"10.1109/VLSIDCS47293.2020.9179931","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179931","url":null,"abstract":"In this paper, we proposed All optical NAND gate using polarization rotation in semiconductor optical amplifier (SOA). We have used Gaussian pulse as a control pulse and simulated the results using MATLAB. The change of extinction ratio (ER) with control and amplified emission noise (ASE) factor is investigated numerically. High value ER shows a clear distinction between low and high state of information.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126505252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Computing Overlapping Signal Influence on Gain Characteristics of EDFA 计算重叠信号对EDFA增益特性的影响
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179925
A. Deyasi, P. Debnath, Soumen Santra
{"title":"Computing Overlapping Signal Influence on Gain Characteristics of EDFA","authors":"A. Deyasi, P. Debnath, Soumen Santra","doi":"10.1109/VLSIDCS47293.2020.9179925","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179925","url":null,"abstract":"Effect of signal overlapping integral and pump overlapping integral are analytically computed for Erbium Doped Fiber Amplifier (EDFA) for gain profile estimation over a longer range of fiber length. Different ranges of the integral functions are taken into account to achieve constant gain, and results are pictorially displayed when fiber length is over 5 m. Under those values of integral functions, doping ion concentration, absorption cross-section and pump local saturation power are independently tuned for the same objective. Interesting result is obtained which speaks that for 5 m fiber length, gain becomes minimum at any practical range of pump saturation power, though it becomes stabilized.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126394549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analytical Modeling for Parasitics in a Triple Gate MOSFET Device 三栅MOSFET器件寄生特性的分析建模
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179934
R. Bose, J. N. Roy
{"title":"Analytical Modeling for Parasitics in a Triple Gate MOSFET Device","authors":"R. Bose, J. N. Roy","doi":"10.1109/VLSIDCS47293.2020.9179934","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179934","url":null,"abstract":"In this paper, simple and analytical models are proposed for a experimental trigate FinFET device which provides a detailed understanding of the inbuilt parasitic resistance and capacitance of the device. The non planar device structures in nano scale regime usually experiences high parasitic resistances and capacitances due to having multiple gates, narrow fin width and narrow source/drain region width as well. A surface potential based charge model is also developed to determine parasitic capacitances. Our proposed model shows good agreement with 3D TCAD Sentaurus device simulation result. The model estimates a limit to scaling of parasitic source/drain resistance and also reveals that contact resistance dominates parasitic resistance of trigate FinFET device.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132313858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analytical Model and Simulation Based Analysis of a Doped Si DG TFET Exhibiting Lower Subthreshold Slope 基于解析模型和仿真的低阈下斜率掺Si DG TFET分析
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179745
Supratim Das
{"title":"Analytical Model and Simulation Based Analysis of a Doped Si DG TFET Exhibiting Lower Subthreshold Slope","authors":"Supratim Das","doi":"10.1109/VLSIDCS47293.2020.9179745","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179745","url":null,"abstract":"A doped double gate uni-junction silicon-based novel Tunnel Field Effect Transistor (TFET) structure is proposed that exhibits lower subthreshold slope (10 mV/decade) and better ON to OFF current ratio (Ion/Ioff is in order of 107 at low supply voltage) compared to conventional double gate TFET structure. A simulation-based analysis of the proposed structure has been carried out with the help of 2D TCAD Sentaurus device simulator at different channel length values. A mathematical model is also developed to verify the result with simulation. Our proposed TFET structure is composed of one common p region which acts as both source and channel. Therefore the configuration is basically a p-n double gate TFET having a n+ pocket close to source side and another n+ pocket close to drain side. These pockets are created separately by using work function engineering technique on metal gate having different lengths and thicknesses and also by using high k and low k dielectric as oxide. The source side n+ pocket enhances tunneling probability thus increasing Ion and Ioff is controlled by another n+ pocket near drain side. Significantly lower subthreshold slope as observed from calibrated simulation of our proposed configuration makes this device more suitable for digital logic application.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"21 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131790809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Verilog Modeling of 24 Bit Stereo DAC Using Multibit SDM 使用多位SDM的24位立体声DAC的Verilog建模
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179880
Saikat RoyChowdhury, Sayantan Sen
{"title":"Verilog Modeling of 24 Bit Stereo DAC Using Multibit SDM","authors":"Saikat RoyChowdhury, Sayantan Sen","doi":"10.1109/VLSIDCS47293.2020.9179880","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179880","url":null,"abstract":"A 24-bit 96kHz sampling rate DAC (Digital-to-Analog Converter) achieves 106dB Dynamic Range. A 3rd order 6bit ∑-∆ modulator is included (SDM). To reduce the sensitivity of the DAC and the non-linearity error we use DWA (Data weighted Averaging) in Dynamic Element Matching Technique (DEM). A 3-bit Quantizer and 3-7 Binary to Thermometric Decoder is introduced in the proposed 24-bit audio DAC. This paper presents stereo input, stereo output and a programmable sampling frequency ranging from 8 kHz to 48 kHz with the help of Verilog Modeling and has done some optimization before implementation. The DAC accepts 16/18/24 bit PCM (Pulse-Code Modulation) data at a sampling rate of 32/44.1/96kHz for applications in CD and DVD audio.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131659357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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