2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)最新文献

筛选
英文 中文
Conduction Mechanism of Polyaniline/Reduced Graphene Oxide/Ag2O Nanocomposite 聚苯胺/还原氧化石墨烯/Ag2O纳米复合材料的导电机理
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179888
Sayantan Sinha, Sumitra Nongthombam, N. A. Devi, S. Rai, R. Bhujel, W. I. Singh, A. Biswas, B. Swain
{"title":"Conduction Mechanism of Polyaniline/Reduced Graphene Oxide/Ag2O Nanocomposite","authors":"Sayantan Sinha, Sumitra Nongthombam, N. A. Devi, S. Rai, R. Bhujel, W. I. Singh, A. Biswas, B. Swain","doi":"10.1109/VLSIDCS47293.2020.9179888","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179888","url":null,"abstract":"Polyaniline/reduced graphene oxide/Ag2O (PANI/rGO/Ag2O) nanocomposite was synthesized using in-situ polymerization technique and characterization was done as XRD, SEM, Raman, FTIR, XPS, UV-vis, and I-V analyses. The morphology as featured by the SEM analysis shows the spherical Ag2O nanoparticles (159-210 nm) anchored on the rGO/Ag2O sheets. The XRD results indicate the presence of Ag2O crystal planes. The D-band Raman peak at 1342 cm-1 attributes to C-C bond vibration suggesting the presence of graphene. The XPS spectrum show the O(1s), N(1s), Ag(3d), and C(1s) core orbital peaks at 529.2 eV, 399.3 eV, 366.5 eV, and 283.1 eV binding energies correspondingly. The reverse bias I-V curve shows non-linear nature and high current for PRGAg120 and diode characteristic but lower current for PRGAg160. The I-V characteristic in forward bias demonstrated non-linear current for PRGAg120 and a similar characteristic for PRGAg160 but with a lesser current.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133977499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluation of Selectivity and Sensitivity of Heterostructure Junction-Less DG-MOSFET Based Biosensor Considering Heating Effect 考虑热效应的异质结构无结DG-MOSFET生物传感器的选择性和灵敏度评价
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179950
Sourav Chakraborty, Dipanjan Sen, Savio Jay Sengupta, Swarnil Roy
{"title":"Evaluation of Selectivity and Sensitivity of Heterostructure Junction-Less DG-MOSFET Based Biosensor Considering Heating Effect","authors":"Sourav Chakraborty, Dipanjan Sen, Savio Jay Sengupta, Swarnil Roy","doi":"10.1109/VLSIDCS47293.2020.9179950","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179950","url":null,"abstract":"In this article, the sensitivity and selectivity of a Si-Ge Hetero-structure Junction-less Double Gate MOSFET (DG-MOSFET) based biosensor has been analyzed by introducing the self-heating issue, when the bio-particles get trapped inside the underlap or cavity region of the sensor. Sensitivity of the proposed device has been analyzed in terms of threshold voltage variation by considering the dielectric modulation method and also by considering the temperature variation. However, the prime focus is to accurately select the temperature range to avoid the performance degradation due to the self-heating issue. Simulation results are obtained by using SILVACO ATLAS tool. So, change in threshold voltage of the device has been considered as the sensing element to study the existence of bio-particles being trapped in the cavity region of the device. Sub-threshold operation has been considered here while analyzing the sensor performance.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"69 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133037164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Spectral Tuning of Gold Nanoparticles Embedded in Dielectric by Changing Anisotropy and Interparticle Interaction: A Mathematical Correlation between the Shape and Interaction 通过改变各向异性和粒子间相互作用嵌入电介质中的金纳米粒子的光谱调谐:形状与相互作用之间的数学关系
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179927
J. K. Majhi
{"title":"Spectral Tuning of Gold Nanoparticles Embedded in Dielectric by Changing Anisotropy and Interparticle Interaction: A Mathematical Correlation between the Shape and Interaction","authors":"J. K. Majhi","doi":"10.1109/VLSIDCS47293.2020.9179927","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179927","url":null,"abstract":"The theoretical studies of optical absorption (OA) properties of anisotropic non-interacting Au nanoparticles (NPs) and the spherical interacting Au NPs embedded in dielectric matrix have been carried out separately. For the studies we have considered a modified Garcia et al. model depend on Maxwell-Garnett (MG) theory where anisotropy of the particles are represented by a parameter β known as shape parameter and interaction is represented by the parameter K. For calculation of OA spectra of anisotropic particles, the values of β is varied from 0.05 to 1.0, considering K = 0 and keeping particle radius fixed at R = 2 nm. The OA spectra of anisotropic Au NPs in the above range of β exhibit a large redshift of surface plasmon resonance (SPR) from 500 - 832 nm in contrary to what is observed for spherical non-interacting particle of same size at an around 520 nm. An exponential type decay of SPR peak position with increase of β has also been observed. The almost similar nature of OA spectra and the decay behavior of the SPR peak with decrease of K have also been observed for interacting spherical Au NPs by varying the interaction parameter K from 20 to 80 of same particle size. The observation gives a correlation between the parameter β and K which was not established. This correlation is essential and helpful for different applications of anisotropic Au nanoparticles in plasmonic, surface enhanced Raman scattering (SERC), photonics, optoelectronics, and others.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115705170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Single-Component Fractional-Order Capacitor Based on Graphene Nanosheet/P(VDF) Composite: Synthesis and Analysis 基于石墨烯纳米片/P(VDF)复合材料的新型单组分分数级电容器:合成与分析
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179871
Zaid Mohammad Shah, F. A. Khanday, Z. A. Jhat
{"title":"A Novel Single-Component Fractional-Order Capacitor Based on Graphene Nanosheet/P(VDF) Composite: Synthesis and Analysis","authors":"Zaid Mohammad Shah, F. A. Khanday, Z. A. Jhat","doi":"10.1109/VLSIDCS47293.2020.9179871","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179871","url":null,"abstract":"Fractional-order capacitor (FOC) is fabricated. The dielectric of the FOC is synthesized using Graphene nanosheets (GNS) as fillers in a P(VDF) matrix. A variety of weight percentages of GNS have been employed in a total of five samples fabricated. Fractional-order behavior is observed for samples having more than 3 wt% loading of GNS in P(VDF) matrix. Nyquist and Bode plots have been provided for the samples. It has been shown that non-ideality is induced with addition of conductive material in P(VDF). FOC characteristics are evident in all the samples with maximum deviation occurring for sample with 9 wt% GNS. Beyond 13 wt% of GNS, conductivity attains constant value. This type of analysis is novel in nature and is a guide to analyze percolated polymer composites.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116107254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Double Gate p-n-p-n TFET with Hetero Oxide Dielectric and High-K Spacer Engineering 双栅p-n-p-n TFET与异质氧化物介电和高k间隔层工程
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179943
Sudipta Ghosh, Prithviraj Pachal, Rahul Kumar, S. Kundu, J. Ghosh, S. Sarkar
{"title":"Double Gate p-n-p-n TFET with Hetero Oxide Dielectric and High-K Spacer Engineering","authors":"Sudipta Ghosh, Prithviraj Pachal, Rahul Kumar, S. Kundu, J. Ghosh, S. Sarkar","doi":"10.1109/VLSIDCS47293.2020.9179943","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179943","url":null,"abstract":"Tunnel Field Transistor (TFET) has emerged as a promising candidate in VLSI industry for low power and high speed applications due to its ability to have subthreshold swing (SS) lesser than 60mV/decade at room temperature. In this work, the performance of a double gate pnpn (DG pnpn) TFET has been studied and the structure is modified with hetero gate dielctric materials in order to enhance its performance. Hetero gate dielctric material is fabricated with HfO2 at the source side followed by SiO2 at the drain side of the oxide material. The same structure is further modulated by introducing high-k spacer both at the source and drain side of the gate oxide. Hafnium Dioxide (HfO2) and Titanium Dioxide (TiO2) have been tested as spacers to observe the performance changes. The proposed structure exhibits a notable surge in Ion current along with reduced Ambipolar conduction with much lower Subtreshold Swing (SS) at room temperature.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116110382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and Analysis of Bulk and Junctionless MOSFET Based Circuits for Low Power Applications 基于MOSFET的低功耗无结体电路的设计与分析
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179929
Saurabh Halder, Rahul Paul, Swarnil Roy
{"title":"Design and Analysis of Bulk and Junctionless MOSFET Based Circuits for Low Power Applications","authors":"Saurabh Halder, Rahul Paul, Swarnil Roy","doi":"10.1109/VLSIDCS47293.2020.9179929","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179929","url":null,"abstract":"The main focus of this work is to study and analyze the Transmission Gate based combinational and sequential digital circuit performance using the Junctionless and BULK technology. The digital circuits chosen for this work are D-FLIP FLOP and MULTIPLEXER. Simulations are done in Tanner EDA and SILVACO. TSMC models of different channel lengths are taken for the measurement of various circuit parameters for BULK case. Finally, a comparison of Junction Less and BULK technology is given.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122539022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Current Reference Circuit Operable at Low Voltages Using Composite MOS Triode Resistor 可在低电压下使用复合MOS三极管电阻的电流基准电路
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179868
K. Sharma, Rahul Kumar Tripathi, H. S. Jatana, R. Pandey, Jaya Madan, Preeti Sharma, Rajnish Sharma
{"title":"Current Reference Circuit Operable at Low Voltages Using Composite MOS Triode Resistor","authors":"K. Sharma, Rahul Kumar Tripathi, H. S. Jatana, R. Pandey, Jaya Madan, Preeti Sharma, Rajnish Sharma","doi":"10.1109/VLSIDCS47293.2020.9179868","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179868","url":null,"abstract":"Invasive biomedical applications involving acquisition and recording of biological signals require current reference generation circuits for low voltage front-end amplifier and filter circuits. However, achieving current reference using Self-Biased Current Source (SBCS) for these circuits at same low supply voltages poses requirement of resistors. In this work, we compare the effect of passive poly resistor and Composite Triode MOS Resistor (CTMR) on the performance of low voltage SBCS circuit using 0.18 µm standard SCL foundry process parameters and models of MOS, capacitor and resistor. For current reference generation of 371 nA, the temperature coefficient (ppm/degree Celsius) values for passive poly resistor and CTMR are 2400 and 2251 respectively. The Figure of Merit, FOM (ppm/degree Celsius) and Coefficient of variance (CV) at different process corners with Monte-carlo simulation (MCS) runs of 100 for CTMR are 0.93 and 0.16 times lower than that of passive poly resistor. The CTMR based SBCS is anticipated to be used in low voltage front-end biomedical applications.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124816891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multi-Stage-Multi-Iterative Optimization Algorithm for Design Optimization of Multi-Quantum Well Terahertz IMPATT Sources 多量子阱太赫兹impt源设计优化的多阶段多迭代优化算法
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179952
S. Chakraborty, A. Acharyya, A. Biswas, A. Kundu
{"title":"Multi-Stage-Multi-Iterative Optimization Algorithm for Design Optimization of Multi-Quantum Well Terahertz IMPATT Sources","authors":"S. Chakraborty, A. Acharyya, A. Biswas, A. Kundu","doi":"10.1109/VLSIDCS47293.2020.9179952","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179952","url":null,"abstract":"A multi-stage-multi-iterative optimization (MSMIO) algorithm has been proposed in this paper for optimizing the design parameters of MQW DDR IMPATT diode based terahertz (THz) sources based on AlxGa1-xN~GaN heterostructures. The optimization has been carried out subject to achieve favourable large-signal (L-S) as well as avalanche noise characteristics of the source designed to operate at 1.0 THz. Six major parameters associated with the MQW structure, such as (i) mole fraction of Al in AlxGa1-xN, (ii) thickness of AlxGa1-xN layers, (iii) corresponding doping concentrations, (iv) thickness of GaN layers, (v) corresponding doping concentrations and (vi) bias current density are optimized subject to attain highest efficiency as well as lowest noise measure of the 1.0 THz source. The L-S and noise characteristics of optimized as well as un-optimized MQW DDR structures are compared in order to verify the proficiency of the algorithm; comparison is also done between simulation and experimental results of 1.0 THz oscillators based on other semiconductors reported earlier.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132278261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
GPSO Hybrid Algorithm for Rectilinear Steiner Tree Optimization 线性斯坦纳树优化的GPSO混合算法
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179861
Subhrapratim Nath, Sagnik Gupta, S. Biswas, Rupam Banerjee, J. Sing, Subir Kumar Sarkar
{"title":"GPSO Hybrid Algorithm for Rectilinear Steiner Tree Optimization","authors":"Subhrapratim Nath, Sagnik Gupta, S. Biswas, Rupam Banerjee, J. Sing, Subir Kumar Sarkar","doi":"10.1109/VLSIDCS47293.2020.9179861","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179861","url":null,"abstract":"Routing is one of the most important stages in the physical layer design of VLSI circuits. The rapid advancement in VLSI technology has necessitated a greater need to optimize the wire length of the circuits i.e. optimize the routing plan. The floor planning and placement strategies manifest a significant effect on the routing plan of a VLSI circuit which in turn requires routing cost optimization. This problem becomes complex when the number of terminal points increases which turns it into an NP-complete problem. In this context, this paper proposes a hybrid metaheuristic optimization algorithm, the Gradient-PSO (GPSO), which hybridizes Gradient Descent and Particle Swarm Optimization for optimization of Rectilinear Steiner Minimal Tree (RSMT).","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129982062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Differential Evolution Algorithm Based Energy Management of Residential Microgrid Under Appliance Scheduling DSM 基于差分进化算法的住宅微电网用电需求管理
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179893
Pritam Chandra, A. Das, Chitresh Das, Aritra Naskar, Biswarup Ganguly, Subho Paul
{"title":"Differential Evolution Algorithm Based Energy Management of Residential Microgrid Under Appliance Scheduling DSM","authors":"Pritam Chandra, A. Das, Chitresh Das, Aritra Naskar, Biswarup Ganguly, Subho Paul","doi":"10.1109/VLSIDCS47293.2020.9179893","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179893","url":null,"abstract":"Depending on the appliance scheduling strategy of the demand side management (DSM), this article elucidates a new mixed-integer linear programming-based method to optimize the operation of a residential microgrid furnished with several deferrable but non-interruptible devices. Unlike previous literatures here flexible loads are not curtailed but delayed and distributed over the entire operation time window, specified by the users. The solution process is designed based on differential evolution (DE) algorithm. Numerical simulation on a practical residential area data proves the efficacy of the proposed strategy in both grid tied and islanded for certain hours scenarios. Further, the simulations results are compared with other heuristic search techniques to prove better performance of DE. Again, convergence of the DE algorithm is validated by linearizing the problem and solved using mixed integer linear programming commercial solver present in MATLAB.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126910722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信