2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)最新文献

Stepped Gate Profiles over DRE TFET: A Proposal to Improve Off-State Breakdown Voltage DRE场效应管上的阶梯栅型:一种提高断态击穿电压的方法

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179878

Upasana, M. Saxena, Mridula Gupta

引用次数: 0

Analysis of All-Optical XNOR Gate in SOA Based Tree-Net Architecture 基于SOA树状网架构的全光XNOR门分析

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179744

A. Raja, K. Mukherjee, J. N. Roy

引用次数: 0

First-Principle Study of Spin Transport in GaAs-Adenine-GaAs Semi-Conductor Tunnel Junction gaas -腺嘌呤- gaas半导体隧道结自旋输运的第一性原理研究

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179864

D. Dey, Pradipta Roy, Debashis De Smieee

引用次数: 2

15W Hybrid GaN Power Amplifier through Microstrip Radial Stub 4W GaN MMIC for X-band Radar Applications 通过微带径向短段的15W混合GaN功率放大器，用于x波段雷达应用

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179860

SriHarsha Vardhan G, Deepali Pathak, Manish Mendhe, A. Dutta

引用次数: 2

Estimation of Power and Delay of CMOS Phase Detector and Phase-Frequency Detector Using Nano Dimensional MOS Transistor 基于纳米尺寸MOS晶体管的CMOS鉴相器和鉴相器的功率和时延估计

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179921

Aman Kumar Shaw Halwai, Ratul Adhikary, M. Chakraborty, Rahul Shaw, Abhijit Sadhu, D. De, Surajit Bari

引用次数: 3

Automated System Design for the Identification of Sleep Disorder: Cross-correlation and SVM Based Approach 睡眠障碍识别的自动化系统设计:互相关与支持向量机方法

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179872

Anadi Biswas, S. Chatterjee, S. Munshi

{"title":"Automated System Design for the Identification of Sleep Disorder: Cross-correlation and SVM Based Approach","authors":"Anadi Biswas, S. Chatterjee, S. Munshi","doi":"10.1109/VLSIDCS47293.2020.9179872","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179872","url":null,"abstract":"In this research work, an automated system is developed for the identification of sleep disorder by analyzing Electroencephalograph (EEG) signals. The EEG signals considered in this study are taken from the Physionet database. The signals have been recorded during the sleeping time of various healthy and unhealthy patients, having sleep disorder. The paper introduces a protocol of feature extraction, involving cross-correlation. The cross-correlation operation automatically eliminates the noises contaminating the electroencephalograph (EEG) signals. The features extracted from the cross-correlograms, besides containing some traditional and not so common parameters, also includes the Higuchi’s Fractal Dimension (HFD). The extracted features from Cross-correlation are processed using Support Vector Machine (SVM), which gives an acceptable accuracy as compare to other research works in bio-signal processing field. The Proposed methodology has achieved 96.65% sensitivity, 100% specificity and 96.67% accuracy. Thus the proposed scheme may be a strong candidate for embedded system applications, where it can be implemented using microcontrollers.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132249874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Fuzzy PID Controlled DSTATCOM for Delivering Quality Power 模糊PID控制DSTATCOM提供优质电能

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179920

Epsita Das, Swaraj Basak, S. Sarkar, Biswarup Ganguly, A. Banerji, S. Biswas

引用次数: 0

TCAD Analysis and Modelling of Gate-Stack Gate All Around Junctionless Silicon NWFET Based Bio-Sensor for Biomedical Application 基于NWFET的全无结硅栅极-堆叠栅极生物传感器的TCAD分析与建模

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179866

Mekonnen Getnet Yirak, R. Chaujar

{"title":"TCAD Analysis and Modelling of Gate-Stack Gate All Around Junctionless Silicon NWFET Based Bio-Sensor for Biomedical Application","authors":"Mekonnen Getnet Yirak, R. Chaujar","doi":"10.1109/VLSIDCS47293.2020.9179866","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179866","url":null,"abstract":"In the present day, metallic oxide semiconductor field-effect transistor-based bio-sensors have been frequently used for various purposes due to their low cost and other properties. In this work, high-k Gate-Stack gate-all-around junctionless Silicon Nanowire FET (SiNWFET) is proposed for neutral biomolecule species detection and enhanced the device performance by introduced gate stack and high metal gate work-function. In particular, neutral biomolecule species like Streptavidin, Uricase, APTES, Protein and ChOx are considered in our study. Subthreshold slope, drain induced barrier lowering (DIBL), leakage current, transconductance, and shifting threshold voltage were considered for study the bio-sensor response. Effect of cavity thickness, cavity length, High-k dielectric thickness, and its length on the detection of the device has also become examined. The results in gate stack junctionless gate all around SiNWFET shows better performance in terms of DIBL, transconductance, leakage current, ION/IOFF ratio and subthreshold slope. The high-k dielectric oxide (HfO2) has been identified for chemical compatibility and thermal stability properties on metal oxide semiconductor transistor as a gate oxide to mitigate the gate tunneling current and short channel effects.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130250603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Design of Area Optimized Arithmetic and Logical Unit for Microcontroller 单片机面积优化算法与逻辑单元的设计

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179942

A. Purohit, Mohammed Riyaz Ahmed, R. V. S. Reddy

{"title":"Design of Area Optimized Arithmetic and Logical Unit for Microcontroller","authors":"A. Purohit, Mohammed Riyaz Ahmed, R. V. S. Reddy","doi":"10.1109/VLSIDCS47293.2020.9179942","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179942","url":null,"abstract":"Arithmetic and Logic Unit (ALU) can be understood with basic knowledge of digital electronics. The advantage of knowing ALU in detail is two-folded: firstly, programming of the processing device can be efficient and secondly, can design a new ALU architecture as per the various constraints of the use cases. The miniaturization of digital circuits can be achieved by either reducing the size of transistor (Moore’s law) or by optimizing the gate count of the circuit. The first has been explored extensively while the latter has been ignored which deals with the application of Boolean rules and requires sound knowledge of logic design. The ultimate outcome is to have an area optimized architecture/approach that optimizes the circuit at gate level. Here in this work, we have attempted to design an ALU which is area efficient while being loaded with additional functionality necessary for microcontrollers. One novel approach in our work is that the concept of hard-wired architecture (for multiplier and divider) is borrowed from Digital Signal Processors. Another aspect worth mentioning is the implementation of barrel shifter which will considerably reduce the execution time during the execution of shift/ rotate operations. The structural modeling is used in the design of the ALU which contributes to the reduction in the usage of number of LUTs and slices. The hardware design is made via Xilinx 9.1 ISE and verified using ModelSim. The results are very encouraging, and it seems that a thorough understanding and proper implementation of ALU will allow us to put other units in their place.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132923350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Gate Engineered GAA Silicon-Nanowire MOSFET for High Switching Performance 高开关性能的栅极工程GAA硅纳米线MOSFET

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179932

N. Gupta, Ajay Kumar, R. Chaujar, Bhavya Kumar, M. M. Tripathi

引用次数: 0