Stepped Gate Profiles over DRE TFET: A Proposal to Improve Off-State Breakdown Voltage

Abstract

The prime focus of this work is towards improving the device off-state breakdown voltage without hampering the on-state resistance value. For this, Drain Region Extended (DRE) TFET architecture has been introduced with stepped gate profiles. The stepped gate profile implementation has been done in two ways. Firstly, the impact of one such previously reported three stepped gate profile has been tested on TFET architecture. Thereafter, a more feasible and cost effective two stepped gate profile has been proposed which helps in improving the device breakdown voltage without hampering other characteristics such as device on-state resistance, on-state current and threshold voltage value. The modified configuration successfully delivers improved breakdown voltage and reduced on-state resistance value and can be used for better functioning in System on Chip (SoC) applications.