Design of Area Optimized Arithmetic and Logical Unit for Microcontroller

Abstract

Arithmetic and Logic Unit (ALU) can be understood with basic knowledge of digital electronics. The advantage of knowing ALU in detail is two-folded: firstly, programming of the processing device can be efficient and secondly, can design a new ALU architecture as per the various constraints of the use cases. The miniaturization of digital circuits can be achieved by either reducing the size of transistor (Moore’s law) or by optimizing the gate count of the circuit. The first has been explored extensively while the latter has been ignored which deals with the application of Boolean rules and requires sound knowledge of logic design. The ultimate outcome is to have an area optimized architecture/approach that optimizes the circuit at gate level. Here in this work, we have attempted to design an ALU which is area efficient while being loaded with additional functionality necessary for microcontrollers. One novel approach in our work is that the concept of hard-wired architecture (for multiplier and divider) is borrowed from Digital Signal Processors. Another aspect worth mentioning is the implementation of barrel shifter which will considerably reduce the execution time during the execution of shift/ rotate operations. The structural modeling is used in the design of the ALU which contributes to the reduction in the usage of number of LUTs and slices. The hardware design is made via Xilinx 9.1 ISE and verified using ModelSim. The results are very encouraging, and it seems that a thorough understanding and proper implementation of ALU will allow us to put other units in their place.