基于纳米尺寸MOS晶体管的CMOS鉴相器和鉴相器的功率和时延估计

Aman Kumar Shaw Halwai, Ratul Adhikary, M. Chakraborty, Rahul Shaw, Abhijit Sadhu, D. De, Surajit Bari
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引用次数: 3

摘要

本文设计了一种基于纳米晶体管的鉴相电路,实现了传统的相频检测电路。利用Tanner SPICE软件对电路原理图进行了仿真。在晶体管栅极长度为16 nm和22 nm时,估计了鉴相电路的功耗、晶体管延迟、功率与延迟的乘积。VDD值在0.5 V ~ 1.2 V范围内变化,PMOS与NMOS的宽高比在1 ~ 5范围内变化,进行了功率和速度性能分析。此外,还给出了该相频检测器在150nm通道长度下的功率、门延迟和PDP值,为高速低功耗的超大规模集成电路的设计提供了参考。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Estimation of Power and Delay of CMOS Phase Detector and Phase-Frequency Detector Using Nano Dimensional MOS Transistor
In this paper the design of phase detector circuit using nano dimensional transistor has been presented .The conventional circuit of phase-frequency detection has been realized and presented. The circuit schematics are simulated with the help of Tanner SPICE software. The power dissipation, transistor delay, product of power and delay of the phase detector circuit has been estimated at 16 nm and 22 nm gate length of transistor. Power and speed performance analysis is carried out varying the value of VDD in the range 0.5 V - 1.2 V and aspect ratio of PMOS to NMOS from 1 to 5 . Moreover, the power, gate delay and PDP of the phase-frequency detector has been stated at 150 nm channel length .The results are pleasing context to the design of Very Large Scale Integrated (VLSI) circuit having high speed and low power dissipation.
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