Gate Engineered GAA Silicon-Nanowire MOSFET for High Switching Performance

Abstract

In this paper, the bias-dependent parasitic capacitance of Gate Engineered GAA SiNW MOSFET is investigated in terms of gate capacitance which take into account both gate to source and gate to drain capacitance. Results depict substantial reduction in parasitic capacitance of gate engineered SiNW MOSFET in comparison to conventional SiNW. Further, RF Figure of Merits (FOMs) has also been observed and it is found that GEWE-SiNW exhibit 8.5%, 14% improvement in fT and TFP respectively compared to SiNW MOSFET, thus provide its efficacy for switching applications such as low power CMOS logic gates and wireless/mobile applications. In addition, the impact of metal workfunction engineering has also been observed to examine the detailed knowledge of device.