Double Gate p-n-p-n TFET with Hetero Oxide Dielectric and High-K Spacer Engineering

Abstract

Tunnel Field Transistor (TFET) has emerged as a promising candidate in VLSI industry for low power and high speed applications due to its ability to have subthreshold swing (SS) lesser than 60mV/decade at room temperature. In this work, the performance of a double gate pnpn (DG pnpn) TFET has been studied and the structure is modified with hetero gate dielctric materials in order to enhance its performance. Hetero gate dielctric material is fabricated with HfO2 at the source side followed by SiO2 at the drain side of the oxide material. The same structure is further modulated by introducing high-k spacer both at the source and drain side of the gate oxide. Hafnium Dioxide (HfO2) and Titanium Dioxide (TiO2) have been tested as spacers to observe the performance changes. The proposed structure exhibits a notable surge in Ion current along with reduced Ambipolar conduction with much lower Subtreshold Swing (SS) at room temperature.