Verilog Modeling of 24 Bit Stereo DAC Using Multibit SDM

Abstract

A 24-bit 96kHz sampling rate DAC (Digital-to-Analog Converter) achieves 106dB Dynamic Range. A 3rd order 6bit ∑-∆ modulator is included (SDM). To reduce the sensitivity of the DAC and the non-linearity error we use DWA (Data weighted Averaging) in Dynamic Element Matching Technique (DEM). A 3-bit Quantizer and 3-7 Binary to Thermometric Decoder is introduced in the proposed 24-bit audio DAC. This paper presents stereo input, stereo output and a programmable sampling frequency ranging from 8 kHz to 48 kHz with the help of Verilog Modeling and has done some optimization before implementation. The DAC accepts 16/18/24 bit PCM (Pulse-Code Modulation) data at a sampling rate of 32/44.1/96kHz for applications in CD and DVD audio.