2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)最新文献_第9页

TCAD Based Optimization of SJ Infrared Solar Cell for an Efficient Thermo-Photovoltaic Application 基于TCAD的SJ红外太阳能电池高效热光伏优化设计

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179849

Dickson Warepam, K. Phimu, Khomdram Jolson Singh, Rudra Sankar Dhar

{"title":"TCAD Based Optimization of SJ Infrared Solar Cell for an Efficient Thermo-Photovoltaic Application","authors":"Dickson Warepam, K. Phimu, Khomdram Jolson Singh, Rudra Sankar Dhar","doi":"10.1109/VLSIDCS47293.2020.9179849","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179849","url":null,"abstract":"A thermophotovoltaic (TPV) cells directly convert infrared (IR) radiation to electricity, similar to when traditional solar cells are exposed to visible light. A reliable high efficient Single junction Infrared cell for thermo-photovoltaic application was modeled by using numerical simulation TCAD tool ATLAS. The most potential materials GaSb, InGaAs and InGaSb and their respective Infrared cell were compared and analyzed their various critical performance parameters. GaSb based TPV cells is found to be the best choice among them. The cell optimization is done for operation with terrestrial solar spectrum AM1.5. The optimized Single Junction Infrared TPV cell is allowed for further increasing the efficiency up to 27.31% at black body spectrum (TBB =1300K). Optimization of doping concentration and layer thickness of GaSb cell with respect to Power conversion efficiency (PCE) and External Quantum Efficiency (EQE) is performed by simple successive iteration algorithm. Further, efficiencies at varied temperature range (1100K to 2000K) is also investigated for future infrared application. It is found that up to 32% efficiency at AM1.5 and 35% efficiency can be attained at 1800K radiation in this proposed optimized cell.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123205454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Stability Analysis of Electric Vehicle Integrated Microgrid for Power Frequency Balance 基于工频平衡的电动汽车集成微电网稳定性分析

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179904

Prasun Sanki, M. Basu, P. Pal

{"title":"Stability Analysis of Electric Vehicle Integrated Microgrid for Power Frequency Balance","authors":"Prasun Sanki, M. Basu, P. Pal","doi":"10.1109/VLSIDCS47293.2020.9179904","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179904","url":null,"abstract":"This paper aims to design the stability margin of an aggregated electric vehicle (EV) for supporting automatic generation control (AGC) operation in an islanded microgrid (IMG) with renewable power producers (RPPs) and energy storage devices (ESDs). Challenge of ensuring better power management while introducing EV in modern power system is the foreground in the IMG system. A groundbreaking attempt has been adopted to determine the stability margin of an aggregated EV model based on its participation, state of charge and power rating. In this context, this proposed work presents a novel proportional integral feedback with proportional derivative (PI-PD) controller for investigating system performance under various conditions. The presence of PD controller in the inner loop ensures better stability enabling the suitable open loop pole placement which assures desirable system response. Over the years, tuning of the controller parameters becomes a new challenge to the researchers. Given this, particle swarm optimization (PSO) is employed here to tune the gain parameters of the controller. Further, comparison studies are also carried out to verify the controller performance. Several case studies are formulated and presented under the MATLAB/Simulink environment to validate the performance of the proposed system configuration.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123373554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Analytical Modeling of Asymmetric Junctionless DMDG MOSFET for Suppressing Short Channel Effects 抑制短通道效应的非对称无结DMDG MOSFET解析建模

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179955

A. Basak, A. Sarkar

引用次数: 0

Design of Telescopic OTA based 6th order Butter-worth Low Pass Filter using 0.18μm CMOS Technology 基于0.18μm CMOS技术的伸缩式OTA六阶黄油值低通滤波器设计

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179746

G. Bhargava, S. Majumdar

引用次数: 1

Sub-threshold Performance Analysis of Multi-Layered Trapezoidal Trench Gate Silicon On Nothing MOSFET for Low Power Applications 低功耗多层梯形沟槽栅无硅MOSFET的亚阈值性能分析

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179957

Sikha Mishra, S. Mohanty, Guru Prasad Mishra

引用次数: 0

Performance Evaluation of Double Gate Pentacene Organic FET Using Simulation Study 双栅并五苯有机场效应晶体管性能的仿真研究

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179743

Ranita Halder, A. Sarkar

引用次数: 0

Performance Analysis of Sub-10nm Vertically Stacked Gate-All-Around FETs 亚10nm垂直堆叠栅极全能场效应管的性能分析

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179913

E. Mohapatra, Tara Prasanna Dash, J. Jena, S. Das, C. K. Maiti

引用次数: 3

Performance Analysis of a Novel Hetero-material InAs/GaAs Junctionless TFET 一种新型异质材料InAs/GaAs无结TFET的性能分析

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179852

Samriti Sharma, R. Chaujar

引用次数: 2

A Low-Power gm-C Filter for Neural Signal Conditioning 一种用于神经信号调理的低功耗gm-C滤波器

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179856

Preeti Sharma, K. Sharma, Jaya Madan, R. Pandey, H. S. Jatana, Rajnish Sharma

{"title":"A Low-Power gm-C Filter for Neural Signal Conditioning","authors":"Preeti Sharma, K. Sharma, Jaya Madan, R. Pandey, H. S. Jatana, Rajnish Sharma","doi":"10.1109/VLSIDCS47293.2020.9179856","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179856","url":null,"abstract":"Neural recording interfaces are being developed to record neuronal activities of the brain for several decades. There is a stringent requirement to provide conditioning to the weak neural signals. However, various analog designers come across a major challenge of lowering down the values of power consumption by the neural signal conditioning stage owing to the noise and bandwidth trade-offs to power. As an anticipated solution to the same, the design of low-noise operational-transconductance amplifier (OTA) - Capacitor filter or gm-C filter capable of passing EEG signals has been presented in this paper. The reported gm-C filter which relies on Gate-Capacitive Bulk-Driven and current-division technique has been implemented in Cadence Analog Design Platform using standard 0.18 μm CMOS process with BSIM3V3 models of transistors. The simulation results indicate that the proposed circuit draws a very low power (0.368 μW) from the power supply of ± 0.5 V with the total-integrated input referred noise voltage of 4.6 μVRMS and -3 dB frequency of 56.2 Hz. The suggested architecture design of the demonstrated conditioning stage may be useful in the field of low-power neuroprosthetic applications.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127486292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Study of Device Performance of Dual Metal Gate Silicon on Insulator MOSFET Adopting Various Dielectric Materials in Gate Oxide 栅极氧化物中采用不同介电材料的双金属栅极硅绝缘子MOSFET器件性能研究

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179873

Anjan Paul, Piyali Saha, T. D. Malakar

{"title":"Study of Device Performance of Dual Metal Gate Silicon on Insulator MOSFET Adopting Various Dielectric Materials in Gate Oxide","authors":"Anjan Paul, Piyali Saha, T. D. Malakar","doi":"10.1109/VLSIDCS47293.2020.9179873","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179873","url":null,"abstract":"An effect of gate oxide material in device operation for the DMG SOI structure has been presented in this paper. It has already been investigated that the DMG silicon on insulator metal oxide field effect transistor is preferable compare to planar one as it reduces various short channel effects. A 2-D analytical modelling of dual material gate SOI structure is established with the help of 2-Dimensional Poisson equation to calculate various device characteristics such as minimum surface potential, electric field, surface potential & threshold voltage etc. In proposed DMG-SOI MOSFET structure we incorporate different gate oxide material having different relative permittivity such as SiO2, HfO2 & TiO2 and a comparative study have been done to measure the impacts of different gate dielectric material on the device performance. It has been observed that higher gate dielectric constant material (TiO2) shows the better device performance as compared to other gate dielectric materials. The results are analyzed with the simulated modelling and explain the validity of present configuration.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133048210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1