{"title":"抑制短通道效应的非对称无结DMDG MOSFET解析建模","authors":"A. Basak, A. Sarkar","doi":"10.1109/VLSIDCS47293.2020.9179955","DOIUrl":null,"url":null,"abstract":"In this paper, an analytical model is proposed for Asymmetric Junctionless dual material double gate (AJDMDG) MOSFETs structure with high K dielectric material for developing electrostatic potential, electric field, front gate threshold voltage (Vth), subthreshold swing (SS). The electrostatic potential is found by solving Poisson’s equation through parabolic approximation method. Moreover, the analytical model is developed for asymmetric nature in device performance through altering back gate oxide thicknesses and voltage. The substantial outcomes of analytical solution are compared with the result of TCAD simulation to validate the device structure. A comparative study has been carried for AJDMDG and junctionless DMDG (JDMDG) MOSFET structure to show the efficacy of asymmetric operation in device performance for suppressing short channel effects (SCEs).","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Analytical Modeling of Asymmetric Junctionless DMDG MOSFET for Suppressing Short Channel Effects\",\"authors\":\"A. Basak, A. Sarkar\",\"doi\":\"10.1109/VLSIDCS47293.2020.9179955\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, an analytical model is proposed for Asymmetric Junctionless dual material double gate (AJDMDG) MOSFETs structure with high K dielectric material for developing electrostatic potential, electric field, front gate threshold voltage (Vth), subthreshold swing (SS). The electrostatic potential is found by solving Poisson’s equation through parabolic approximation method. Moreover, the analytical model is developed for asymmetric nature in device performance through altering back gate oxide thicknesses and voltage. The substantial outcomes of analytical solution are compared with the result of TCAD simulation to validate the device structure. A comparative study has been carried for AJDMDG and junctionless DMDG (JDMDG) MOSFET structure to show the efficacy of asymmetric operation in device performance for suppressing short channel effects (SCEs).\",\"PeriodicalId\":446218,\"journal\":{\"name\":\"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIDCS47293.2020.9179955\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIDCS47293.2020.9179955","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analytical Modeling of Asymmetric Junctionless DMDG MOSFET for Suppressing Short Channel Effects
In this paper, an analytical model is proposed for Asymmetric Junctionless dual material double gate (AJDMDG) MOSFETs structure with high K dielectric material for developing electrostatic potential, electric field, front gate threshold voltage (Vth), subthreshold swing (SS). The electrostatic potential is found by solving Poisson’s equation through parabolic approximation method. Moreover, the analytical model is developed for asymmetric nature in device performance through altering back gate oxide thicknesses and voltage. The substantial outcomes of analytical solution are compared with the result of TCAD simulation to validate the device structure. A comparative study has been carried for AJDMDG and junctionless DMDG (JDMDG) MOSFET structure to show the efficacy of asymmetric operation in device performance for suppressing short channel effects (SCEs).