Analytical Modeling for Parasitics in a Triple Gate MOSFET Device

Abstract

In this paper, simple and analytical models are proposed for a experimental trigate FinFET device which provides a detailed understanding of the inbuilt parasitic resistance and capacitance of the device. The non planar device structures in nano scale regime usually experiences high parasitic resistances and capacitances due to having multiple gates, narrow fin width and narrow source/drain region width as well. A surface potential based charge model is also developed to determine parasitic capacitances. Our proposed model shows good agreement with 3D TCAD Sentaurus device simulation result. The model estimates a limit to scaling of parasitic source/drain resistance and also reveals that contact resistance dominates parasitic resistance of trigate FinFET device.