2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)最新文献_第8页

Investigation of Pb-free solder interconnect under drop impact by ball pull and shear tests 通过球拉和剪切试验研究跌落冲击下无铅焊料互连的性能

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490674

S. Chung, Mi-Jin Kim

引用次数: 2

Predicting crack initiation and propagation using XFEM, CZM and peridynamics: A comparative study 用XFEM、CZM和周动力学方法预测裂纹萌生和扩展的比较研究

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490851

A. Agwai, I. Guven, E. Madenci

引用次数: 22

Sensitivity analysis of Pb free reflow profile parameters toward flip chip on silicon assembly yield, reliability and intermetallic compound characteristics 无铅回流曲线参数对倒装芯片成品率、可靠性和金属间化合物特性的敏感性分析

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490844

Zhaozhi Li, Sangil Lee, B. Lewis, P. Houston, D. Baldwin, G. Stout, T. Tessier, John L. Evans

{"title":"Sensitivity analysis of Pb free reflow profile parameters toward flip chip on silicon assembly yield, reliability and intermetallic compound characteristics","authors":"Zhaozhi Li, Sangil Lee, B. Lewis, P. Houston, D. Baldwin, G. Stout, T. Tessier, John L. Evans","doi":"10.1109/ECTC.2010.5490844","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490844","url":null,"abstract":"Flip chip process excels due to its low cost, fine pitch, small form factor and its ready-adaptation to the conventional Surface Mount Technology (SMT) process, in the fact that the reflow is often used to form the solder joint. As the use of Pb free solder is legislated today, it is vital to understand the impact of reflow process conditions on the formation of the flip chip solder joint, so that the assembly process of the flip chip can be better controlled. This paper introduces a comprehensive experimental study on the impact of Pb free reflow profile parameters towards flip chip on silicon assembly solder joint formation characteristics as well as the reliability performance. The reflow parameters studied include the soak time, peak temperature and time above liquidus. Three levels of each reflow parameter are investigated. The Response Surface Methodology (RSM) is used for Design of Experiment (DOE) to explore the quadratic effect of the investigated parameters. Results studied include the package assembly yield, package shear strength, intermetallic compound thickness as well as the package reliability performance. Study results show that the fine pitch flip chip on silicon package has a wide reflow process window to achieve 100% yield, if reflowed in a Nitrogen environment. Yield loss was found when the packages are reflowed in air. With the fifteen reflow profiles studied, it was found that the reflow parameters are not significant in terms of the package shear strength. For the intermetallic compound thickness, it was found that the time above liquidus is a significant factor, with a 99.9% confidence level. No statistical difference was found among packages assembled under different reflow conditions up to 2500 liquid to liquid thermal shock reliability testing.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129289413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Analysis of carbon nanotube based Through Silicon Vias 基于硅通孔的碳纳米管分析

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490885

S. Kannan, Anurag Gupta, Bruce C. Kim, F. Mohammed, Byoungchul Ahn

引用次数: 26

Effect of temperature on transition in failure modes for high speed impact test of solder joint and comparison with board level drop test 温度对焊点高速冲击试验失效模式转变的影响及与板面跌落试验的比较

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490685

Pradosh Guruprasad, J. Pitarresi, B. Sykes

引用次数: 3

Effects of thermal cycling parameters on lifetimes and failure mechanism of solder interconnections 热循环参数对焊料互连寿命及失效机理的影响

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490910

T. Mattila, H. Xu, O. Ratia, M. Paulasto-Krockel

{"title":"Effects of thermal cycling parameters on lifetimes and failure mechanism of solder interconnections","authors":"T. Mattila, H. Xu, O. Ratia, M. Paulasto-Krockel","doi":"10.1109/ECTC.2010.5490910","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490910","url":null,"abstract":"The work presented in this paper focuses on a) clarifying the underlying physical failure mechanism of Sn-rich solder interconnections under thermomechanical loading and b) identifying the means to accelerate the failure mechanism by optimizing the dwell-times and ramp-rates of thermal cycling test. The statistical results showed that as the dwell-times were decreased the number of cycles to failure increased but the shortest testing time was achieved with 10-minute dwell-times. Increase of ramp-rate did not affect the number of cycles to failure but the time to failure was significantly reduced. Investigations of the nucleation of cracks in solder interconnections revealed that nucleation is much more dependent on the number of thermal cycles than on the studied test parameters and that the nucleation took place within about the first quarter of the average lifetimes. Furthermore, cracking of the SnAgCu interconnections under all thermal cycling conditions studied took place through the bulk of the solder interconnections along the continuous network of grain boundaries produced by recrystallization. An approach to further accelerate thermal cycling tests is proposed based on the formed understanding of the failure mechanism.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116347902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Non-wet solder joint detection in processor sockets and BGA assemblies 处理器插座和BGA组件的非湿式焊点检测

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490846

A. F. Said, B. Bennett, F. Toth, Lina Karam, J. Pettinato

{"title":"Non-wet solder joint detection in processor sockets and BGA assemblies","authors":"A. F. Said, B. Bennett, F. Toth, Lina Karam, J. Pettinato","doi":"10.1109/ECTC.2010.5490846","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490846","url":null,"abstract":"The existence of non-wet solder joints in PCB sockets can cause boards failures and it's necessary to inspect theses sockets to locate any possible defective joints. 2D or advanced x-ray machines are used to image solder joints in processor sockets and make solder joints visible to be examined by the operator who determines if each individual joint is defective or not. This is a very time consuming process since each processor has an average of 150 images with 30 joints per image. An accurate and efficient non-wet detection method is proposed in this paper. The main components of the proposed method consist of region of interest (ROI) segmentation, feature extraction, reference-free classification, and automatic mapping. The ROI segmentation process is a noise-resilient segmentation method for the joint area. The centroids of the segmented joints (ROIs) are used as feature parameters to detect the suspect joints. The proposed reference-free classification can detect defective joints with high accuracy without the need for training data. An automatic mapping method is used to get the precise label and location of the suspect joint. The accuracy of the proposed method was determined to be 95.8% detection rate with 1.1% false alarm rate based on the examination of 56 sockets (500K joints). In comparison, the detection rates of currently available advanced x-ray tools with multi-dimension capability are in the range of 43% to 75%. The proposed method reduces the operator effort by 90%. The presented system identifies neighboring joints to any missed non-wet joints, which provides an operator with the capability to make 100% detection of all non-wets. The proposed scheme works with a 2D x-ray imaging device, which makes the proposed scheme relatively inexpensive to implement, and is very portable and easy to set up as compared to the available advanced x-ray tools with multi-dimension capability.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115600270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Room-temperature chip-stack interconnection using compliant bumps and wedge-incorporated electrodes 室温芯片堆叠互连使用兼容凸起和楔形集成电极

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490730

N. Watanabe, T. Asano

引用次数: 5

TSV manufacturing yield and hidden costs for 3D IC integration 3D集成电路的TSV制造良率与隐性成本

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490828

J. Lau

引用次数: 153

Micro tube insertion into indium, copper and other materials for 3D applications 微管插入到铟，铜等材料的3D应用

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490732

B. G. de Brugiere, F. Marion, M. Fendler, V. Mandrillon, A. Hazotte, M. Volpert, H. Ribot

引用次数: 4