2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)最新文献

Extending lower-cost packaging technology into next generation signaling: Techniques and considerations 将低成本封装技术扩展到下一代信号:技术和考虑

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490809

M. Doyle, J. Bartley, R. Ericson, M. Bailey, P. Germann, G. Zettles

{"title":"Extending lower-cost packaging technology into next generation signaling: Techniques and considerations","authors":"M. Doyle, J. Bartley, R. Ericson, M. Bailey, P. Germann, G. Zettles","doi":"10.1109/ECTC.2010.5490809","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490809","url":null,"abstract":"Current industry trends, combined with present cost pressures shall force signal integrity engineers to revisit traditional “rules of thumb” such that additional bandwidth can be obtained from conventional (standard) packaging materials and methodologies. In this paper, the authors assert that some current design practices prematurely cap the useful bandwidth of current technology, and unnecessarily lead designers to ask material scientists to solve our bandwidth concerns. Every facet of the electronics industry is subject to cost pressures. Opposite these financial constraints is the continuing drive to improve performance. Every new product must evaluate the business case for the use or inclusion of a new technology, more expensive component, or increase in power. The larger design community tends to move together into and out of technology “nodes” as they become more feasible and cost effective. Whether or not a particular technology is effective at meeting the design and business goals is a function of what other technologies and consequences are traded off in order to use it. This paper examines the conventional wisdom of some common practices, in light of an attempt to forego the use of advanced packaging technologies while extending the practical life of lower-cost techniques to signaling interfaces with higher frequency content.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116937427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects 三维互连无缺陷镀铜和硅通孔化学机械抛光的集成工艺

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490731

D. Malta, C. Gregory, D. Temple, T. Knutson, Chen Wang, T. Richardson, Yun Zhang, R. Rhoades

{"title":"Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects","authors":"D. Malta, C. Gregory, D. Temple, T. Knutson, Chen Wang, T. Richardson, Yun Zhang, R. Rhoades","doi":"10.1109/ECTC.2010.5490731","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490731","url":null,"abstract":"The fabrication of through-silicon vias (TSVs) is a major component in the development of three-dimensional (3D) integration technology and advanced 3D packaging approaches. The large diameter and length of TSVs, as compared to traditional interconnects, create some unique process challenges. Via plating and chemical-mechanical polishing (CMP) processes used in standard copper interconnect technology are generally not suitable for TSV fabrication. Therefore, efforts are being made to develop such processes specifically for TSV technology. This paper will describe the development of a void-free Cu electroplating process for TSV filling, along with CMP processing to remove the overburden layer and expose the Cu-filled vias for subsequent metallization. The focus of the paper will be the integration of the TSV plating and CMP processes, with discussion regarding observed integration challenges and their solutions. First, a Cu electroplating process was developed for defect-free, bottom-up filling of silicon vias from 20–200µm in diameter and 150–375µm deep, with aspect ratios from 1:1 to 8:1. Next, CMP tests were conducted using Cu-filled silicon vias of 50µm diameter and 150µm depth, designed for use in a MEMS wafer-level packaging application. These tests indicated that plating nonuniformity and Cu mound defects over filled vias caused significant CMP process issues. The plating process was then modified to eliminate these problems in the Cu films, resulting in improved CMP uniformity and reduced polishing time.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124765886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Design, process integration and characterization of wafer level vacuum packaging for MEMS resonator MEMS谐振器晶圆级真空封装的设计、制程整合与表征

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490754

A. Yu, C. Premachandran, R. Nagarajan, C.W. Kyoung, Lam Quynh Trang, Rakesh Kumar, L. Lim, J. H. Han, Yap Guan Jie, P. Damaruganath

{"title":"Design, process integration and characterization of wafer level vacuum packaging for MEMS resonator","authors":"A. Yu, C. Premachandran, R. Nagarajan, C.W. Kyoung, Lam Quynh Trang, Rakesh Kumar, L. Lim, J. H. Han, Yap Guan Jie, P. Damaruganath","doi":"10.1109/ECTC.2010.5490754","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490754","url":null,"abstract":"This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter material. The MEMS resonator is fabricated and characterized in a vacuum chamber. Relationship between the Q-factor of the MEMS resonator and the vacuum level is established and used as a reference for later vacuum level calibration. Wafer bonding using evaporated AuSn solder is performed in an EVG wafer bonder. With optimized bonding conditions, the achieved shear strength is higher than 59 MPa and uniform cross-section of the bonding ring has been achieved. The calculated He leakage rate is between 10−13 atm cc/s and 10−14 atm cc/s. By comparing the measured Q-factor of packaged resonator with the reference curve, the corresponding vacuum level is 0.2 Torr. Reliability tests results show that shear strength decreases for 7% and still high enough for real application. The vacuum level after reliability tests is comparable to that of long term vacuum level.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125839240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Investigation of bump crack and deformation on Pb-free flip chip packages 无铅倒装芯片封装的碰撞裂纹和变形研究

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490791

Jeremias P. Libres, J. C. Arroyo

{"title":"Investigation of bump crack and deformation on Pb-free flip chip packages","authors":"Jeremias P. Libres, J. C. Arroyo","doi":"10.1109/ECTC.2010.5490791","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490791","url":null,"abstract":"The demand for die to package interconnects free of Pb in the next generation flip chip packages requires a flux and underfill solution that meets package reliability requirements. Bump cracks and bump deformation were observed during temperature cycling on large body, full Pb-free ceramic flip chip BGA packages during initial package development. The phenomenon is considered unique in terms of its nature and failure mechanism. Traditional bump crack issues are concentrated at or near the silicon and underfill interfaces. In this case, cracks occurred within the bulk solder away from either silicon or substrate interface. Failed bumps also showed severe deformation. In addition, morphology differences in the underfill material surrounding the affected bumps provided important clues as to the nature of the failure mechanism. An extensive investigation to understand the root cause of the unique bump crack issue in the bulk solder, which covered both process and material-related factors, resulted in a clear understanding of the failure mechanism and the implementation of an effective solution to the problem. This manuscript describes the relationship of the flux residue-underfill interaction, the localized change in underfill properties due to the flux residues, and eventually the impact of this change on the bump integrity during package stressing. These findings made it possible to establish a good flux-underfill selection methodology to achieve a robust Pb-free package solution that is being implemented in next generation flip chip products.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114911941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Temperature dependence of thin film spiral inductors on Alumina over a temperature range of 25 to 475° C 氧化铝薄膜螺旋电感在25至475°C温度范围内的温度依赖性

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490775

G. Ponchak, J. Jordan, M. Scardelletti

引用次数: 14

Inkjet printed organic transistors for sustainable electronics 用于可持续电子学的喷墨印刷有机晶体管

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490659

G. Orecchini, R. Zhang, J. Agar, D. Staiculescu, M. Tentzeris, L. Roselli, C. Wong

{"title":"Inkjet printed organic transistors for sustainable electronics","authors":"G. Orecchini, R. Zhang, J. Agar, D. Staiculescu, M. Tentzeris, L. Roselli, C. Wong","doi":"10.1109/ECTC.2010.5490659","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490659","url":null,"abstract":"Embedded paper electronics is a promising solution for the future of electronics, and thus the goal for this paper is to show the pathway toward achieving inkjet solutions for the realization of complex circuitry on the cheapest synthetic material made by humankind: PAPER. A direct write technology, inkjet printing transfers the designed pattern directly to the substrate. Inkjet technologies have gained a lot of ground as a more accurate and economic fabrication method than traditional lithography. The challenge of this work is to identify the right materials and to show the printability of all the building blocks of an organic field-effect transistor (OTFT). For the semiconductor, a highly soluble pentacene precursor, 13,6-N-Sulfinylacetamidopentacene, is proposed. Anisole, a high boiling point solvent is chosen to insure proper jetting of the solution. The solution jets well and it has to be used right after preparation as its printability degrades with time. For the gate dielectric, two solutions are proposed: (i) using the paper itself as an insulator and print a bottom gate device on both sides of a double sided glossy paper, (ii) a pentacene impurity, of 6,13-pentacenequinone (PQ), in a top gate configuration, which may improve the device mobility by reducing the scattering sites at the semiconductor-dielectric interface. For the electrodes, a printable nano-particle based silver ink has to be modified to match the work function with pentacene, or replaced with an alternate printable material like Carbon Nanotubes (CNTs). Preliminary electrical testing of the pentacene film printed directly on paper shows good conduction properties for a 25 µm channel length. Further improvement of the pentacene film performance is proposed. This work establishes the foundation for the first fully printed OTFT on paper.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115568740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

A study of package warpage for package on package (PoP) 包对包(PoP)包装翘曲的研究

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490967

M. Amagai, Yutaka Suzuki

引用次数: 22

An investigation of reliability and solder joint microstructure evolution of select Pb-free FCBGA pad finish and solder ball alloy combinations 选择无铅FCBGA焊面和焊球合金组合的可靠性和焊点组织演变研究

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490723

D. Cavasin

{"title":"An investigation of reliability and solder joint microstructure evolution of select Pb-free FCBGA pad finish and solder ball alloy combinations","authors":"D. Cavasin","doi":"10.1109/ECTC.2010.5490723","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490723","url":null,"abstract":"As Pb-free packaging technologies evolve, increased emphasis has been placed on the development of robust mechanical and metallurgical solutions. A number of different component and PCB surface finish options are now widely available, as are several different BGA solder ball alloys. Similarly, various different Pb-free C4 bumping alloys are being introduced, compounding the need for clear understanding of how the resulting interconnect systems stand up to the normal rigors of end-user applications. This paper focuses on the component-level reliability and metallurgical evolution of the C4 (flip chip) and BGA interconnect systems formed by the combination of commonly specified surface finishes and BGA solder alloys. The two surface finishes selected were electroless Ni/electroless Pd/immersion Au (ENEPIG), and immersion Sn (IT). The selected BGA alloys were Sn-3Ag-0.5Cu (SAC305) and Sn-3.5Ag. All four of these alloy/pad finish combinations were found to pass the various industry-standard (JEDEC) reliability stress tests without any failures, as measured through open/short testing and CSAM analyses of the packages. However, significant differences in microstructural evolution of the solder/substrate interfaces were observed.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114046012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Comparative study of PWB pad cratering subject to reflow soldering and thermal impact 回流焊与热冲击对PWB焊盘成形的影响

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490929

Chaoran Yang, F. Song, S. Lee, K. Newman

引用次数: 10

Fracture mechanics of lead-free solder joints under cyclic shear load 循环剪切载荷作用下无铅焊点断裂力学

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490928

Huili Xu, W. Bang, Hongtao Ma, Tae-Kyu Lee, K. Liu, C. Kim

引用次数: 6