2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)最新文献_第10页

Inductance properties of silicon-in-grown horizontal carbon nanotubes 硅生长水平碳纳米管的电感特性

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490649

Minghui Sun, Zhiyong Xiao, Y. Chai, Yuan Li, P. Chan

引用次数: 4

High-speed parallel interface implementation with low-cost system solution by using signal integrity factorial design 采用信号完整性析因设计实现低成本高速并行接口

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490696

J. Hsu, Sam Yang, Wei-Da Guo, R. Lee, Tung-Yang Chen

引用次数: 0

High power and fine pitch assembly using solder Anisotropic Conductive Films (ACFs) combined with ultrasonic bonding technique 采用各向异性焊料导电膜(ACFs)结合超声键合技术实现高功率、高间距组装

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490937

Kiwon Lee, K. Paik

{"title":"High power and fine pitch assembly using solder Anisotropic Conductive Films (ACFs) combined with ultrasonic bonding technique","authors":"Kiwon Lee, K. Paik","doi":"10.1109/ECTC.2010.5490937","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490937","url":null,"abstract":"In this study, in order to improve the electrical properties and the reliability of ACF joints, we propose the simultaneous fluxless solder joining and adhesive bonding technology. This technology utilizes fluxless soldering within an adhesive matrix on metal electrodes combined with room temperature ultrasonic (U/S) ACF bonding technique advantages. According to the experimental results, the temperature of the solder ACF joints showed rapid heating rates up to 400 °C/s and peak values above 250°C by applying ultrasonic vibration. The ACF temperature could be precisely controlled ranging from 75°C to 260°C by adjusting U/S vibration amplitudes from 4 um to 13 um. At above the melting temperatures of solder particles, U/S bonded solder ACF joints showed higher than 80% soldering ratios and no void formation with optimized U/S parameters. The soldering ratio at the solder ACF joints increased as the ACF temperature increased and it was presumably due to the viscosity decrease of the ACF adhesive matrix. On the other hand, thermocompression (T/C) bonded solder ACF joints showed poor soldering ratios lower than 30% and severe void formation at above 200°C. At the same time, U/S bonded solder ACF joints showed 30% reduced electrical contact resistances and twice better reliability in an unbiased autoclave test (121°C, 2 atm, 100%RH) compared with conventional ACF joints. Significance of this result is that fluxless solder joining and adhesive bonding can be simultaneously achieved within 5 seconds by using solder ACFs combined with the room temperature U/S bonding technique.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126585163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

An evaluation of die crack risk of over-molded packages due to external impact 外部冲击对过模件模具裂纹风险的评价

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490767

P. Su, Boaz Khan, Min Ding

{"title":"An evaluation of die crack risk of over-molded packages due to external impact","authors":"P. Su, Boaz Khan, Min Ding","doi":"10.1109/ECTC.2010.5490767","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490767","url":null,"abstract":"Component failures due to physical damage to the silicon are occasionally observed on board assembly processes. Such failures typically are not detected until electrical testing is performed at the end of the process, making it challenging to identify where and how such damages could occur. While process steps are designed to apply the lowest force possible on components, excessive load can be introduced by unexpected events such as machine malfunction or accidental external impact. For over-molded packages, particularly for packages with a large die and thin mold cap thickness, protection for such abnormal impact is reduced and even low levels of force can induce damage to the silicon. In this work, impact test is performed on two types of over-molded packages that have different die and package geometries. External load is applied on the top of the packages through the drop of a probe from different heights. The damages induced in the silicon are evaluated with ultrasonic scan and cross-section. The results from these analytical steps will help identify the threshold force for the die crack failures. A finite element model is constructed to simulate the impact test for one of the packages. The time-history of the load is analyzed and the maximum stress levels in the silicon for the different drop heights are compared. Two different mold cap thicknesses are also simulated. By comparing the stress levels from the model and the real-life testing results, we are able to obtain general guidelines for the maximal impact allowed for the package investigated in this study and provide references for analysis of future failures.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130206608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A novel wafer level bonding/debonding technique using an anti-adhesion layer for polymer-based zero-level packaging of RF device 一种新的晶圆级键合/脱键技术，用于射频器件的聚合物零级封装

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490954

J. Kim, S. Seok, N. Rolland, P. Rolland

引用次数: 12

Pd effects on the reliability in the low cost Ag bonding wire 钯对低成本银焊线可靠性的影响

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490789

J. Cho, Kyeong-Ah Yoo, S. Hong, J. Moon, Yong-Je Lee, Wongil Han, Hanki Park, S. Ha, Seong-Bum Son, S. Kang, K. Oh

{"title":"Pd effects on the reliability in the low cost Ag bonding wire","authors":"J. Cho, Kyeong-Ah Yoo, S. Hong, J. Moon, Yong-Je Lee, Wongil Han, Hanki Park, S. Ha, Seong-Bum Son, S. Kang, K. Oh","doi":"10.1109/ECTC.2010.5490789","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490789","url":null,"abstract":"Recently, the application of Ag bonding wires in electronic devices has been attempted as alternative to Au bonding wires to reduce the material cost of Au. Nevertheless, Ag bonding wires have not been applied to devices due to interface corrosion problems between the Ag wire and Al pad during humidity reliability tests, such as the PCT (Pressure Cooker Test). As the technology for alloying Pd element in Ag wire has developed recently, the corrosive failure problem at the interface in the PCT has been improved significantly. This study examined the behavior of IMCs(intermetallic compounds) and interface corrosion between an Ag wire and Al metallization under humidity conditions (100%RH, 121'C). The chemical compositions of the Ag wires tested were pure Ag, Ag — 1wt%Pd and Ag-3%Pd. These wires are bonded to Al and noble metal(Au, Pd) metallization using a thermo-sonic bonder. The interfaces were characterized by FIB(Focused ion beam), HRTEM (High Resolution Transmission Electron Microscope) and EDS (Energy Dispersive X-ray Spectroscopy) The findings show that, (1) the interfacial reliability between the Ag wire and Ag metallization was improved considerably. The interface corrosion was suppressed significantly as the Pd content was increased. (2) Ag wires on a noble metal(Au, Pd) pad have stable reliability in PCT.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123012705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Investigation of Pb-free solder interconnect under drop impact by ball pull and shear tests 通过球拉和剪切试验研究跌落冲击下无铅焊料互连的性能

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490674

S. Chung, Mi-Jin Kim

引用次数: 2

Predicting crack initiation and propagation using XFEM, CZM and peridynamics: A comparative study 用XFEM、CZM和周动力学方法预测裂纹萌生和扩展的比较研究

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490851

A. Agwai, I. Guven, E. Madenci

引用次数: 22

Sensitivity analysis of Pb free reflow profile parameters toward flip chip on silicon assembly yield, reliability and intermetallic compound characteristics 无铅回流曲线参数对倒装芯片成品率、可靠性和金属间化合物特性的敏感性分析

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490844

Zhaozhi Li, Sangil Lee, B. Lewis, P. Houston, D. Baldwin, G. Stout, T. Tessier, John L. Evans

{"title":"Sensitivity analysis of Pb free reflow profile parameters toward flip chip on silicon assembly yield, reliability and intermetallic compound characteristics","authors":"Zhaozhi Li, Sangil Lee, B. Lewis, P. Houston, D. Baldwin, G. Stout, T. Tessier, John L. Evans","doi":"10.1109/ECTC.2010.5490844","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490844","url":null,"abstract":"Flip chip process excels due to its low cost, fine pitch, small form factor and its ready-adaptation to the conventional Surface Mount Technology (SMT) process, in the fact that the reflow is often used to form the solder joint. As the use of Pb free solder is legislated today, it is vital to understand the impact of reflow process conditions on the formation of the flip chip solder joint, so that the assembly process of the flip chip can be better controlled. This paper introduces a comprehensive experimental study on the impact of Pb free reflow profile parameters towards flip chip on silicon assembly solder joint formation characteristics as well as the reliability performance. The reflow parameters studied include the soak time, peak temperature and time above liquidus. Three levels of each reflow parameter are investigated. The Response Surface Methodology (RSM) is used for Design of Experiment (DOE) to explore the quadratic effect of the investigated parameters. Results studied include the package assembly yield, package shear strength, intermetallic compound thickness as well as the package reliability performance. Study results show that the fine pitch flip chip on silicon package has a wide reflow process window to achieve 100% yield, if reflowed in a Nitrogen environment. Yield loss was found when the packages are reflowed in air. With the fifteen reflow profiles studied, it was found that the reflow parameters are not significant in terms of the package shear strength. For the intermetallic compound thickness, it was found that the time above liquidus is a significant factor, with a 99.9% confidence level. No statistical difference was found among packages assembled under different reflow conditions up to 2500 liquid to liquid thermal shock reliability testing.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129289413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Analysis of carbon nanotube based Through Silicon Vias 基于硅通孔的碳纳米管分析

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490885

S. Kannan, Anurag Gupta, Bruce C. Kim, F. Mohammed, Byoungchul Ahn

引用次数: 26