Wafer level embedded System in Package (WL-eSiP) for mobile applications

Abstract

Recently, System in Package (SiP) technology is rapidly evolved from a narrow set of applications to high volume applications on electronics markets, like small modules for mobile phone applications. Embedding technology is one of the solutions by embedding one or more chips into another chip or a substrate. In this study, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level flip-chip bonding technology, wafer level molding for under-filling and encapsulation by molding compound without any special substrate have been developed, including redistribution, solder and Cu bumping, thinning and ball mounting technology. Firstly to verify and optimize structure and materials through stress simulation for molded dies, maximum stress and its location have been confirmed and correlated with the result of reliability evaluation using molded die sample. The structure and materials for WL-eSiP has been optimized through molded die samples with evaluation of the reliability tests of MSL2a, PCT (121 °C/ 100%RH/ 2atm), TC (−40/125 °C) and HTS (150°C) in terms of various die size, dielectric and mold materials. Using the results achieved above, WL-eSiP test vehicle has been designed and fabricated to evaluate the package level and board level reliabilities for verifying process and ensuring package reliability. Mother chip of 4mm × 4mm and daughter chip of 2.95mm × 2.31mm size have been designed in daisy chain pattern to be electrically interconnected each other. First of all, whole manufacturing process steps of wafer level embedded system in package (WL-eSiP) has been verified and developed, with redistribution, high aspect-ratio copper bumping, wafer level flip-chip bonding, wafer level molding, silicon and mold thinning and ball mounting technologies. Then, WL-eSiP has been fabricated for evaluation of package level reliability, MSL3, PCT (121°C/100%RH/ 2atm), TC (-40/125°C) and HTS (150°C) and all items have been passed. For the board level reliability test, daisy chain substrate has been designed and fabricated for TC (−40/125°C) and drop (1500G/ 0.5ms) tests. Besides, in order to increase the mother chip size from 16 mm2 to 36 mm2 for the expansion of application of WL-eSiP, stress improvement on each process step has been done through warpage and curvature evaluation on wafer level.