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Proceedings of the European Conference on Design Automation.最新文献

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Formal method for self-timed design 自定时设计的形式化方法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206389
M. Kishinevsky, A. Kondratyev, A. Taubin
{"title":"Formal method for self-timed design","authors":"M. Kishinevsky, A. Kondratyev, A. Taubin","doi":"10.1109/EDAC.1991.206389","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206389","url":null,"abstract":"A formal method of self-timed circuit design, based on compact event model-change diagrams (CD), is suggested. This model (CD) seems to be very attractive because of convenient tools for describing the semantics of concurrency which allows one to enhance the specification from distributive class of processes to semimodular ones. The necessary and sufficient conditions of CD correctness and polynomial algorithms of their analysis are introduced. The formal synthesis procedure consider as the set of equivalent transformations of initial specification (inserting to it the additional signals) that exclude some incorrectness (contradiction, abnormality and so on). The Boolean equations of implementing self-timed circuit can be easily obtained from the corrected description.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125647592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Optimization of microcontrollers by partitioning 通过分区优化微控制器
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206427
G. Tarroux, B. Rouzeyre, G. Sagnes
{"title":"Optimization of microcontrollers by partitioning","authors":"G. Tarroux, B. Rouzeyre, G. Sagnes","doi":"10.1109/EDAC.1991.206427","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206427","url":null,"abstract":"Presents a new partitioning method for finite state machines (FSMs). The method is particularly well suited for mu -controller circuits. It consists in grouping the mu -instructions of the control graph into classes according to a compatibility property of the output values. Only one sequence of output values is then generated for all mu -instructions of a given class. The resulting structure is composed of three machines: a state machine which generates the next states, a command machine and a filter machine. The command outputs and the filter outputs are merged via a logical AND to obtain the final outputs. This structure leads to an area reduction of 34% to 65% for the examples presented.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133820420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fast functional evaluation of candidate OBDD variable orderings 候选OBDD变量排序的快速函数评估
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206348
D. Ross, K. Butler, R. Kapur, M. R. Mercer
{"title":"Fast functional evaluation of candidate OBDD variable orderings","authors":"D. Ross, K. Butler, R. Kapur, M. R. Mercer","doi":"10.1109/EDAC.1991.206348","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206348","url":null,"abstract":"Symbolic simulation via ordered binary decision diagrams (OBDDs) is becoming more feasible each year. These representations are often very efficient under an appropriate ordering of the variables of the functions represented. Recently, heuristics for ordering variables have been developed, but due to the nature of heuristics, no single heuristic always produces an appropriate ordering. The authors develop and analyze a technique for selecting the best of several candidate orderings. The ordering selection method is fast. Its ranking of an ordering is compared to the actual performance of an ordering during functionals (OBDD) calculations in circuits from the ISCAS85 combinational benchmarks. Compared to any previously published single ordering heuristic, the method allows OBDD calculations using less cumulative memory over all six circuits investigated, and also produces over an order of magnitude improvement for one or more of these circuits, over every single heuristic examined.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131534180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A framework for hierarchical performance analysis (of VLSI) 一种(VLSI的)分层性能分析框架
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206437
F.M. Saadi, B. Kaminska
{"title":"A framework for hierarchical performance analysis (of VLSI)","authors":"F.M. Saadi, B. Kaminska","doi":"10.1109/EDAC.1991.206437","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206437","url":null,"abstract":"The performance analysis of VLSI integrated circuits (ICs) with flat tools is slow and even sometimes impossible to complete. Some hierarchical tools have been developed to speed up the analysis of these large ICs. However, these hierarchical tools suffer from a poor interaction with the CAD database and poorly automatized operations. The authors introduce a general hierarchical framework for performance analysis to solve these problems. The circuit analysis is automatic under the proposed framework. Information that has been automatically abstracted in the hierarchy is kept in database properties along with the topological information. A limited software implementation of the framework, PREDICT, has also been developed to analyze the delay performance.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131119577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Specification of timing constraints for controller synthesis 控制器综合时序约束规范
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206415
Rumi Zahir, W. Fichtner
{"title":"Specification of timing constraints for controller synthesis","authors":"Rumi Zahir, W. Fichtner","doi":"10.1109/EDAC.1991.206415","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206415","url":null,"abstract":"For controller synthesis to be successful, detailed knowledge of the timing constraints of the system under synthesis is essential. The authors present a method for extracting timing constraints from a behavioral description, architectural restrictions, component timing requirements and protocol specifications. The timing constraints are combined in a timing constraint graph that can be solved in polynomial time using algorithms known from symbolic layout compaction.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115507271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
MACHETE: synthesis of sequential machines for easy testability MACHETE:综合顺序机器，便于测试
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206410
B. Vinnakota, N. Jha
{"title":"MACHETE: synthesis of sequential machines for easy testability","authors":"B. Vinnakota, N. Jha","doi":"10.1109/EDAC.1991.206410","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206410","url":null,"abstract":"Test generation for sequential machines is known to be computationally expensive. The authors present a scheme, called MACHETE (MACHines for Easy TEstability), for synthesizing easily testable architectures for sequential machines by adding some state transitions and their associated output vectors to the state transition table. This is done to make the internal states of the machine easily controllable as well as observable. This can enable us to obtain a high fault coverage in reasonable amounts of CPU time.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117043893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
TAS: an accurate timing analyser for CMOS VLSI TAS:用于CMOS VLSI的精确定时分析仪
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206404
A. Hajjar, A. Greiner, R. Marbot, Payam Kiani
{"title":"TAS: an accurate timing analyser for CMOS VLSI","authors":"A. Hajjar, A. Greiner, R. Marbot, Payam Kiani","doi":"10.1109/EDAC.1991.206404","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206404","url":null,"abstract":"A CMOS timing analyser using accurate delay models is presented. Switch-level analytic delays are derived from I/V characteristics of short-channel MOSFETS. A significant improvement in accuracy is obtained from the analysis of pertinent capacitances, modeling conflicts and slope effects in CMOS gates. The program handles large-scale circuits and gives the worst-case delays between circuit terminals in realistic CPU times. The algorithm for path analysis is described. It is concluded that the run time is linear with the number of transistors, the accuracy within 5% over a wide range of design types.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130690335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Delay estimation for CMOS functional cells CMOS功能单元的延迟估计
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206369
J. Madsen
{"title":"Delay estimation for CMOS functional cells","authors":"J. Madsen","doi":"10.1109/EDAC.1991.206369","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206369","url":null,"abstract":"Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128938079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A self-checking PLA automatic generator tool based on unordered codes encoding 基于无序码编码的自检PLA自动生成工具
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206459
K. Torki, M. Nicolaidis, A. O. Fernandes
{"title":"A self-checking PLA automatic generator tool based on unordered codes encoding","authors":"K. Torki, M. Nicolaidis, A. O. Fernandes","doi":"10.1109/EDAC.1991.206459","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206459","url":null,"abstract":"Self-checking circuits ensure concurrent error detection by means of hardware redundancy. An important drawback of self-checking circuits is the fact that they involve a significant increasing of the design time. Specific CAD tools are needed in order to cope with this drawback. In this paper the authors present a tool allowing automatic generation of self-checking PLAs. Then they validate this tool by transforming a set of PLA benchmarks into self-checking PLAs and give statistics concerning the required area overhead.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130895250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Parallel switch-level simulation for VLSI VLSI并行开关级仿真
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206417
R. Mueller-Thuns, D. Saab, J. Abraham
{"title":"Parallel switch-level simulation for VLSI","authors":"R. Mueller-Thuns, D. Saab, J. Abraham","doi":"10.1109/EDAC.1991.206417","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206417","url":null,"abstract":"Switch-level simulation is widely used in the design verification process of Very Large Scale Integrated (VLSI) MOS circuits. In this paper, the authors present methods for accelerating switch-level simulation by mapping it onto general purpose parallel computers. Their target machines are medium-grain multiprocessors (shared memory or message passing machines) and they only consider model parallel computation, where the model of the design to be simulated is partitioned among processors. Efficient strategies are introduced for circuit partitioning as well as the corresponding simulation algorithms. In the authors' approach, they try to minimize the total number of synchronizations between processors, as well as ensure portability and scalability. A preprocessor and simulator were implemented and good performance was obtained for a set of benchmarks. The problem of tight coupling between processors that evaluate a strongly connected component in the circuit in a distributed fashion is highlighted.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134643769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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