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Proceedings of the European Conference on Design Automation.最新文献

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Circuit partitioning into small sets: a tool to support testing with further applications 电路划分成小的集:一个工具，以支持测试与进一步的应用
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206461
S. Tragoudas, R. Farrell, F. Makedon
{"title":"Circuit partitioning into small sets: a tool to support testing with further applications","authors":"S. Tragoudas, R. Farrell, F. Makedon","doi":"10.1109/EDAC.1991.206461","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206461","url":null,"abstract":"The authors consider a general partitioning problem, namely how to partition the elements of a circuit into sets of size less than a small constant, so that the number of nets which connect elements in different sets is minimized. One application is in the design for testability of VLSI chips and printed circuit boards. The authors consider two different versions of a bottom-up iterative approach. In the first version they present an efficient heuristic. In an alternative version, the heuristic is used as a subroutine to an approximation (provably good) algorithm, resulting in comparably good solutions. The authors compare both approaches with the familiar top-down approach which uses a well known bisection heuristic as a subroutine. These solutions outperform the top-down partitioning approach.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128089631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A fast and efficient algorithm for determining fanout trees in large networks 一种快速有效的大型网络扇出树确定算法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206466
Shen Lin, M. Marek-Sadowska
{"title":"A fast and efficient algorithm for determining fanout trees in large networks","authors":"Shen Lin, M. Marek-Sadowska","doi":"10.1109/EDAC.1991.206466","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206466","url":null,"abstract":"The authors present a heuristic algorithm the optimal selection of the fanout tree structures in VLSI circuit design. The algorithm minimizes area of the added buffers under the specified timing constraints. The algorithms described in the literatures solve a simpler problem of minimizing the circuit's timing without taking into account the area increase introduced by the buffers. Experimental results demonstrate that the authors' approach is very fast and efficient, particularly for large examples whose solution spaces are very large.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132069280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Why to incorporate a data definition language into a CAD frameworks extension language 为什么要将数据定义语言合并到CAD框架扩展语言中
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206356
K. Gröning, W. Heijenga
{"title":"Why to incorporate a data definition language into a CAD frameworks extension language","authors":"K. Gröning, W. Heijenga","doi":"10.1109/EDAC.1991.206356","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206356","url":null,"abstract":"Discusses extension languages for CAD frameworks. The authors show that the incorporation of a data definition language (DDL) not only makes sense but is a must for a serious extension language, if it intends to meet all requirements that occur in CAD frameworks. To illustrate this approach the authors introduce TIDL (tool integration description language), a representative for an extension language with an incorporated DDL.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116908720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
GRTL-a graphical platform for pipelined system design grtl -一个用于流水线系统设计的图形化平台
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206439
G. Jennings
{"title":"GRTL-a graphical platform for pipelined system design","authors":"G. Jennings","doi":"10.1109/EDAC.1991.206439","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206439","url":null,"abstract":"Presents GRTL, a graphical design tool specifically for manual design of synchronous pipelines at the register transfer level. Abstractions (parameterized behavioral components, abstract signals) and AI methodology simplify input and reduce detail, yet useful timing analyses can be obtained. Features include integrated interactive design blackboard, Werner diagram and clocking formalisms for design correctness, open library, reversible functional simulator, and down-loading facility for external silicon compilation. Earlier work is contrasted.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117027557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Array folding using heuristics and simulated annealing 基于启发式和模拟退火的阵列折叠
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206390
L. N. Kannan, D. Sarma
{"title":"Array folding using heuristics and simulated annealing","authors":"L. N. Kannan, D. Sarma","doi":"10.1109/EDAC.1991.206390","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206390","url":null,"abstract":"Array folding is a technique to reduce the area of a logic array by exploiting its sparsity. Since the problem is NP-complete, heuristic algorithms that yield a near optimal solution have to be employed. In this paper, a method employing a combination of simulated annealing and heuristic algorithms has been used to find a near optimal solution for both simple and multiple folding of logic arrays. The algorithms developed have been implemented in a computer program called GAMIN-SA. When compared to PLEASURE, GAMIN-SA was seen to perform as good or better with regard to quality of solution and, for the bigger arrays, it was better in terms of run-time as well (multiple folding).<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126305302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
LAST: a layout area and shape function estimator for high level applications LAST:用于高级应用的布局区域和形状函数估计器
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206423
F. Kurdahi, C. Ramachandran
{"title":"LAST: a layout area and shape function estimator for high level applications","authors":"F. Kurdahi, C. Ramachandran","doi":"10.1109/EDAC.1991.206423","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206423","url":null,"abstract":"The author addresses the problem of area prediction of VLSI layouts. They present an approach based on two models, analytical and constructive. A circuit design is recursively partitioned down to a level specified by the user thus generating a slicing tree. An analytical model is then used to predict the shape functions of the leaf subcircuits. By traversing the tree bottom up the shape function of the entire layout design can then be constructively predicted. This approach permits the user to trade off the accuracy of the prediction versus the run time of the predictor. Such a scheme is quite useful for high-level synthesis and system level partitioning. The experimental validation results are quite good, indicating an average error of the order of 5% in predicting shape functions for standard cell benchmark designs with sizes ranging from 125 to 12000 cells.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"390 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126744941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Glue-logic partitioning for floorplans with a rectilinear datapath 具有直线数据路径的平面图的胶水逻辑分区
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206382
A. Wu, D. Gajski
{"title":"Glue-logic partitioning for floorplans with a rectilinear datapath","authors":"A. Wu, D. Gajski","doi":"10.1109/EDAC.1991.206382","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206382","url":null,"abstract":"Describes a novel glue-logic partitioning algorithm for floorplan generation in a constrained rectilinear area. This algorithm dissects the layout area into area blocks according to the given module aspect ratio. The algorithm estimates the transistor capacity for each area block, and then uses a seed-based multiway partitioning strategy to assign glue-logic components into area blocks. The algorithm runs iteratively and selects the partition with the minimum total area as the final floorplan. The examples demonstrate the algorithm's suitability for top-down hierarchical physical design.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126151308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Data flow graphs: system specification with the most unrestricted semantics 数据流图:具有最不受限制语义的系统规范
Proceedings of the European Conference on Design Automation. Pub Date : 1900-01-01 DOI: 10.1109/EDAC.1991.206434
G. de Jong
{"title":"Data flow graphs: system specification with the most unrestricted semantics","authors":"G. de Jong","doi":"10.1109/EDAC.1991.206434","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206434","url":null,"abstract":"A new data flow graph concept is defined to be used for architectural synthesis as well as verification of a system. The graph contains only the explicit data dependencies, but any other constraints can also be described. The semantics of this graph does not impose any restriction on the scheduler, except for the explicit data dependencies. For instance, the scheduler is not forced to work on certain blocks in the graph, like loop bodies but may work also across these borders. It is also proved that an optimal schedule can be found efficiently.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122492618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Clock independent timing verification of level-sensitive latches 电平敏感锁存器的时钟独立定时验证
Proceedings of the European Conference on Design Automation. Pub Date : 1900-01-01 DOI: 10.1109/EDAC.1991.206406
R. Tjarnstrom
{"title":"Clock independent timing verification of level-sensitive latches","authors":"R. Tjarnstrom","doi":"10.1109/EDAC.1991.206406","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206406","url":null,"abstract":"The author presents a method to automatically handle level-sensitive latches in timing analysis/verification. Timing specifications, including delays and timing constraints, are automatically generated for the cells in the design. The generated timing specifications are independent of clocking strategy, since clock and data are treated equally. Conditional constraints and paths are used to capture the transparent property of latches. The constraint rules are based on electrical/physical laws instead of assumptions about design styles. Timing errors due to clock skew and improper design are detected.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115892490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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