LAST: a layout area and shape function estimator for high level applications

Abstract

The author addresses the problem of area prediction of VLSI layouts. They present an approach based on two models, analytical and constructive. A circuit design is recursively partitioned down to a level specified by the user thus generating a slicing tree. An analytical model is then used to predict the shape functions of the leaf subcircuits. By traversing the tree bottom up the shape function of the entire layout design can then be constructively predicted. This approach permits the user to trade off the accuracy of the prediction versus the run time of the predictor. Such a scheme is quite useful for high-level synthesis and system level partitioning. The experimental validation results are quite good, indicating an average error of the order of 5% in predicting shape functions for standard cell benchmark designs with sizes ranging from 125 to 12000 cells.<>