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Proceedings of the European Conference on Design Automation.最新文献

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Tool communication in an integrated synthesis environment 集成合成环境中的工具通信
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206353
B. Kleinjohann, E. Kupitz
{"title":"Tool communication in an integrated synthesis environment","authors":"B. Kleinjohann, E. Kupitz","doi":"10.1109/EDAC.1991.206353","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206353","url":null,"abstract":"A tight integration strategy developed during the realization of a hardware synthesis system is described. It allows online visualization of data changes caused for example by a synthesis tool. Common data schemes for various design views were designed. For manipulation of each design view one abstract data type is provided, avoiding redundant implementations. Communication structures for concurrent manipulation of common data structures were developed. The system architecture allows easy system extension/configuration.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1875 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116904492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Interactive symbolic distortion analysis of analogue integrated circuits 模拟集成电路的交互式符号失真分析
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206453
P. Wambacq, G. Gielen, W. Sansen
{"title":"Interactive symbolic distortion analysis of analogue integrated circuits","authors":"P. Wambacq, G. Gielen, W. Sansen","doi":"10.1109/EDAC.1991.206453","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206453","url":null,"abstract":"A program is presented that generates symbolic expressions for the harmonic distortion, caused by weak nonlinearities in continuous-time analogue integrated circuits. The program relies upon the theory of Volterra series. An approximation algorithm with a user-definable error enhances the interpretability of the expressions. The results are in good agreement with results from a numerical simulator. The program can be used to analyse complex circuits such as operational amplifiers and to develop guidelines for low-distortion circuit design.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117212630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Periodic signal suppression in a concurrent fault simulator 并发故障模拟器中的周期性信号抑制
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206471
T. Weber, F. Somenzi
{"title":"Periodic signal suppression in a concurrent fault simulator","authors":"T. Weber, F. Somenzi","doi":"10.1109/EDAC.1991.206471","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206471","url":null,"abstract":"Clock suppression has been proposed to take advantage of the periodic signals such as the clock present in synchronous designs. In clock suppression, no events due to the clock input are generated, but the information can be reconstructed as needed. In this paper, the authors present periodic signal suppression, which is a generalized form of clock suppression, as a means to suppress predictable events of all periodic signals throughout the circuit. To do this, a special signal state labeled P is introduced. P states indicate that signals are periodic, but cause no unnecessary activity in an event driven simulator. At any time, the original waveform can be reconstructed from the periodic signal. This general implementation allows clock suppression to work on divided or gated clocks and on signals that may alternate periodic and non-periodic behavior in addition to the clock tree. Moreover, concurrent simulation of faults on the suppressed signal wires including the clock tree is possible.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128726008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
PHIDEO: a silicon compiler for high speed algorithms PHIDEO:用于高速算法的硅编译器
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206442
P. Lippens, J. V. Meerbergen, A. V. D. Werf, W. Verhaegh, B. McSweeney, J. Huisken, O. McArdle
{"title":"PHIDEO: a silicon compiler for high speed algorithms","authors":"P. Lippens, J. V. Meerbergen, A. V. D. Werf, W. Verhaegh, B. McSweeney, J. Huisken, O. McArdle","doi":"10.1109/EDAC.1991.206442","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206442","url":null,"abstract":"PHIDEO is a silicon compiler targeted at the design of high performance real time systems with high sampling frequencies such as HDTV. It supports the complete design trajectory starting from a high level specification all the way down to layout. New techniques are used to perform global optimisations across loop boundaries in hierarchical flow graphs. The compiler is based on a new target architectural model. Apart from the datapaths special attention is paid to memory optimisation. The new techniques are demonstrated using a progressive scan conversion algorithm.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129149275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 141
An automatic synthesizer for CMOS operational amplifiers 用于CMOS运算放大器的自动合成器
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206450
C. Kuo, Liang-Gee Chen, T. Parng
{"title":"An automatic synthesizer for CMOS operational amplifiers","authors":"C. Kuo, Liang-Gee Chen, T. Parng","doi":"10.1109/EDAC.1991.206450","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206450","url":null,"abstract":"A design methodology with a good trade-off between design time and quality in the automatic synthesis of CMOS operational amplifiers is presented. It is based on an iterative device sizing approach in which a multivariate interpolation technique provides a way to improve the design and the SPICE simulator gives quantitative evaluation of the resultant circuit performance in each design iteration. The methodology has been implemented and proved to be very practical and promising.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114322495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
PLATO-a CAD tool for logic synthesis based on decomposition 基于分解的逻辑合成CAD工具
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206361
T. Luba, J. Kalinowski, Krzysztof Jasinski
{"title":"PLATO-a CAD tool for logic synthesis based on decomposition","authors":"T. Luba, J. Kalinowski, Krzysztof Jasinski","doi":"10.1109/EDAC.1991.206361","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206361","url":null,"abstract":"A CAD system for logic synthesis (PLATO system) that exploits logic decomposition to optimize the actual circuit is presented. Unlike the traditional approach, where the partitioning or decomposition follows logic minimization, decomposition process is carried out in the PLATO system as the very first step in the logic synthesis. Experimental results indicate that a significant reduction of the silicon area can be obtained using this new design strategy.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121503102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
On L*n Boolean matrices with all L*k submatrices having 2/sup k/ distinct row vectors 在L*n个布尔矩阵上所有L*k个子矩阵有2/sup k个不同的行向量
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206463
Hongzhong Wu
{"title":"On L*n Boolean matrices with all L*k submatrices having 2/sup k/ distinct row vectors","authors":"Hongzhong Wu","doi":"10.1109/EDAC.1991.206463","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206463","url":null,"abstract":"The author describes a new method to construct an L*n boolean matrix for two given integers n and k (k<n), such that every L*k submatrix contains 2/sup k/ distinct row vectors of","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"IA-21 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132532667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a persistent programming environment in an object oriented language using clustering and composite objects 使用集群和复合对象，用面向对象语言设计持久性编程环境
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206446
M. Sim, P. Dewilde
{"title":"Design of a persistent programming environment in an object oriented language using clustering and composite objects","authors":"M. Sim, P. Dewilde","doi":"10.1109/EDAC.1991.206446","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206446","url":null,"abstract":"Describes how the object oriented and persistent paradigms are incorporated in a generic system for creating a persistent environment that interfaces between tools defined in a conventional object oriented language and a DBMS. The system is based on a software library of classes that together form a mechanism that can manage configurations of structured and unstructured data and can be employed recursively to define and manage composite objects.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133060291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A probabilistic fault model for analog faults 模拟故障的概率故障模型
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206365
M. Favalli, P. Olivo, B. Riccò
{"title":"A probabilistic fault model for analog faults","authors":"M. Favalli, P. Olivo, B. Riccò","doi":"10.1109/EDAC.1991.206365","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206365","url":null,"abstract":"Presents a probabilistic approach to the detection of analog faults (i.e. transistors stuck-on and bridgings) in CMOS circuits that depends on the conductances of faulty and fault-free networks. In particular, all conductances are considered as random variables with normal distribution. Conductance distributions of complex conflicting networks can be easily evaluated and the detection probability of each fault is determined. The expected coverage of analog faults is known at the end of a fault simulation. This result is shown to be more realistic than those obtained in a deterministic way.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123471874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The VLSI-programming language Tangram and its translation into handshake circuits vlsi编程语言七巧板及其在握手电路中的翻译
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206431
K. V. Berkel, J. Kessels, M. Roncken, Ronald Saeijs, F. Schalij
{"title":"The VLSI-programming language Tangram and its translation into handshake circuits","authors":"K. V. Berkel, J. Kessels, M. Roncken, Ronald Saeijs, F. Schalij","doi":"10.1109/EDAC.1991.206431","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206431","url":null,"abstract":"Views VLSI design as a programming activity. VLSI designs are described in the algorithmic programming language Tangram. The paper gives an overview of Tangram, providing sufficient detail to invite the reader to try a small VLSI program himself. Tangram programs can be translated into handshake circuits, networks of elementary components that interact by handshake signaling. The authors have constructed a silicon compiler that automates this translation and converts these handshake circuits into asynchronous circuits and subsequently into VLSI layouts.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"11 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120861649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 234
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