A probabilistic fault model for analog faults

Presents a probabilistic approach to the detection of analog faults (i.e. transistors stuck-on and bridgings) in CMOS circuits that depends on the conductances of faulty and fault-free networks. In particular, all conductances are considered as random variables with normal distribution. Conductance distributions of complex conflicting networks can be easily evaluated and the detection probability of each fault is determined. The expected coverage of analog faults is known at the end of a fault simulation. This result is shown to be more realistic than those obtained in a deterministic way.<>