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Proceedings of the European Conference on Design Automation.最新文献

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Improved force-directed scheduling 改进了力导向调度
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206441
W. Verhaegh, E. Aarts, J. Korst, P. Lippens
{"title":"Improved force-directed scheduling","authors":"W. Verhaegh, E. Aarts, J. Korst, P. Lippens","doi":"10.1109/EDAC.1991.206441","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206441","url":null,"abstract":"Presents a mathematical justification of the technique of force-directed scheduling and propose two modifications of the basic algorithm introduced by Paulin and Knight. The newly presented modifications improve the effectiveness of force-directed scheduling without affecting its time complexity. This is illustrated by an empirical performance analysis based on a number of problem instances.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125008805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Correct interactive transformational synthesis of DSP hardware 正确的DSP硬件交互变换合成
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206350
F. Burns, D. Kinniment, A. Koelmans
{"title":"Correct interactive transformational synthesis of DSP hardware","authors":"F. Burns, D. Kinniment, A. Koelmans","doi":"10.1109/EDAC.1991.206350","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206350","url":null,"abstract":"Presents a new interactive tool for the guided synthesis of digital signal processing hardware. The tool is driven from a HDL. It will suggest different ways of implementing different architectures for the same specification, maintaining the correctness of implementations during the design process. The tool will automatically generate input for the Boyer Moore theorem prover from the HDL specification in order to verify the correctness of the implementations.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129693150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Goal orientated slicing enumeration through shape function clipping 通过形状函数裁剪实现面向目标的切片枚举
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206425
G. Sigl, Ulf Schlichtmann
{"title":"Goal orientated slicing enumeration through shape function clipping","authors":"G. Sigl, Ulf Schlichtmann","doi":"10.1109/EDAC.1991.206425","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206425","url":null,"abstract":"Two new methods for efficient enumeration of slicing structures useful for macro cell and sea-of-gates final placement are presented. Contrary to existing approaches a further preorder traversal of the slicing tree is added, which allows elimination of unnecessary shapes in an early design phase. Applying this look ahead strategy, memory and computation time requirements have been reduced drastically. Better placements have been achieved by using the saved resources to enlarge the search space for enumeration.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128498267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Symbolic implication in test generation 测试生成中的符号含义
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206456
S. Kundu, I. Nair, L. Huisman, V. Iyengar
{"title":"Symbolic implication in test generation","authors":"S. Kundu, I. Nair, L. Huisman, V. Iyengar","doi":"10.1109/EDAC.1991.206456","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206456","url":null,"abstract":"All test generation algorithms make use of symbolic algebra. The symbolic value that most test generators use is 'X', to denote the unknown/do not care logic value. The other end of the spectrum is to shade each X differently to fully exploit the information contained in them. This is impractical due to combinatorial explosion that results from such coloring. In this paper, the authors explore use of limited symbolic evaluation in test generation. This symbolic evaluation greatly improves test generation compared with the usual five-valued simulation. Also, and in contrast with other established techniques in test pattern generation such as static learning and dynamic learning, it requires no preprocessing and almost no additional memory.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129545550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Electrical modelling of lossy on-chip multilevel interconnecting lines 有损片上多层互连线路的电气建模
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206370
K. Z. Dimopoulos, J. Avaritsiotis, S. J. White
{"title":"Electrical modelling of lossy on-chip multilevel interconnecting lines","authors":"K. Z. Dimopoulos, J. Avaritsiotis, S. J. White","doi":"10.1109/EDAC.1991.206370","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206370","url":null,"abstract":"A self contained method for the electrical modelling of lossy 3-D multilevel interconnections has been developed. The method allows for the generation of a multiple coupled line model, compatible with SPICE-like CAD programs, from the interconnection line constants and parasitic coupling parameters which are computed by the so-called method of moments. The proposed method can be used for the analysis of coupled line systems with linear or nonlinear/time varying terminators, as well as for the study of the pulse propagation characteristics in high-speed ICs. Numerical results are presented for 3-D parallel and galvanically separated crossed planar lines.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"05 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129919009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An integrated layout system for sea-of-gates module generation 闸门模块生成集成布局系统
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206398
P. Duchene, M. Declercq, S. M. Kang
{"title":"An integrated layout system for sea-of-gates module generation","authors":"P. Duchene, M. Declercq, S. M. Kang","doi":"10.1109/EDAC.1991.206398","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206398","url":null,"abstract":"Presents a sea-of-gates layout system able to design medium-size logic circuits in a true channelless fashion. The methodology relies on flexible leaf cell generation, systematic cell terminal abutment, a global routine scheme using integer linear programming methods, and a step-wise compaction-rerouting refinement. Modules up to several hundred transistors have been laid out compactly with more than 80% transistor utilization with two layers of metal. With top-down hierarchy, those modules can be used as macrocells.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130879889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment 为Cathedral-II/2nd架构合成环境自动生成测试模式
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206392
J. V. Sas, F. Catthoor, Peter Vandeput, Frank Rossaert, H. Man
{"title":"Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment","authors":"J. V. Sas, F. Catthoor, Peter Vandeput, Frank Rossaert, H. Man","doi":"10.1109/EDAC.1991.206392","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206392","url":null,"abstract":"The CAD implementation of a testability strategy for chips as designed with the Cathedral-II/2nd silicon compilation environment is presented. Emphasis is on the software tools accomplishing the test assembly. These tools are fully integrated with synthesis, place and route and module generation programs. The hierarchy present in the design has been exploited to assemble the test patterns in an hierarchical way. The authors' approach allows to arrive at a fully testable chip, with a very high fault coverage.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125603061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Testability analysis of hierarchical finite state machines 层次有限状态机的可测试性分析
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206411
Françoise Martinolle, J. Geffroy, B. Soulas
{"title":"Testability analysis of hierarchical finite state machines","authors":"Françoise Martinolle, J. Geffroy, B. Soulas","doi":"10.1109/EDAC.1991.206411","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206411","url":null,"abstract":"The authors present a hierarchical analysis of interconnected finite state machines helpful for testability evaluation. Formal operators determine the controllable and observable functional parts of the modules of the hierarchy; several kinds of functional redundancies are deduced and their causes are diagnosed. A prototype written in PROLOG validates these concepts.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114012280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Datapath optimization using feedback 使用反馈的数据路径优化
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206375
D. Knapp
{"title":"Datapath optimization using feedback","authors":"D. Knapp","doi":"10.1109/EDAC.1991.206375","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206375","url":null,"abstract":"Describes recent experience with Fasolt, a software tool that automatically optimizes a register-level datapath. Fasolt uses a model of layout to drive the choice of optimizing transformations at the levels of scheduling and allocation; hence it is a feedback-driven optimization system. In choosing transformations, Fasolt takes placement and wiring into account in a way that has not been demonstrated in any other high-level synthesis system. Fasolt is also cyclic in that high-level transformations trigger changes at lower levels, which after analysis trigger further high-level changes. This implementation of Fasolt has an expanded set of transformation rules, timing-driven and area-driven transformations, and improved layout modeling capability. The authors present experimental results on three basic test cases and two major variations on the layout software.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122626722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Synthesis of fully testable sequential machines 完全可测试顺序机的综合
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206409
R. Thomas, S. Kundu
{"title":"Synthesis of fully testable sequential machines","authors":"R. Thomas, S. Kundu","doi":"10.1109/EDAC.1991.206409","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206409","url":null,"abstract":"A circuit consists of logic and memory elements. Testing of a circuit involves testing both. Typically, it takes long input sequences to initialize memory elements. Without initialization of memory elements, testing is not possible. In the classical approach to design for test, such as scan design, modifications are made to the circuit to obtain easy and full controllability and observability of the memory elements. The author addresses the design for testability issue for non-scan designs, where both controllability and observabilities are reduced. In the process one ends up with a design that is also suitable for concurrent checking. Concurrent checking is a verification process, which is performed concomitantly with normal operation. The technique described here incurs an area overhead but almost no performance penalty.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131414873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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