Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment

Abstract

The CAD implementation of a testability strategy for chips as designed with the Cathedral-II/2nd silicon compilation environment is presented. Emphasis is on the software tools accomplishing the test assembly. These tools are fully integrated with synthesis, place and route and module generation programs. The hierarchy present in the design has been exploited to assemble the test patterns in an hierarchical way. The authors' approach allows to arrive at a fully testable chip, with a very high fault coverage.<>