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Proceedings of the European Conference on Design Automation.最新文献

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SHARP-looking geometric partitioning 锐利的几何分割
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206384
S. Bapat, J. Cohoon
{"title":"SHARP-looking geometric partitioning","authors":"S. Bapat, J. Cohoon","doi":"10.1109/EDAC.1991.206384","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206384","url":null,"abstract":"A new technique, named SHARP, is presented for the partitioning of VLSI integrated circuits. SHARP is a hill-climbing heuristic that is designed to be incorporated into a partitioning-based placement algorithm. Its important features include a geometric decomposition of the layout surface into a ' Hash '-shaped region; a multi-objective function that more accurately represents wire usage than the standard min-cut criterion, and extensive use of Steiner trees. A series of experiments demonstrates that the SHARP technique produces very high quality partitions.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134290127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator Eldo-XL:通过模拟模拟器分析数字MOS电路的软件加速器
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206377
J. Besnard, J. Benkoski, B. Hennion
{"title":"Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator","authors":"J. Besnard, J. Benkoski, B. Hennion","doi":"10.1109/EDAC.1991.206377","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206377","url":null,"abstract":"Eldo-XL is composed of a set of techniques developed on the basis of the Eldo analog simulator and integrated in it. Eldo-XL is targeted at the simulation of MOS digital circuits with minimal loss of accuracy compared to Eldo. The basis of Eldo-XL is a simpler MOS transistor model which allows the analytical solution of the nodal equations most of the time. The costly iterations associated the implicit solution are avoided and a large speed-up is obtained. The availability of a simpler relaxation algorithm can further enhance the performance on circuits with little feedback. All these acceleration techniques can be used on the digital part of a mixed analog/digital circuit without influencing the accuracy of the solution of the analog part. This paper presents the three techniques developed for Eldo-XL and attempts to show that a good efficiency can be reached without losing generality by combining a classical analog simulator with a dedicated evaluation engine for digital MOS circuits.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"91 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134100289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
PHIFACT-a design space exploration program 一个设计空间探索程序
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206359
F. Crowet, M. Davio, C. Dierieck, J. Durieu, G. Louis, C. Ykman-Couvreur
{"title":"PHIFACT-a design space exploration program","authors":"F. Crowet, M. Davio, C. Dierieck, J. Durieu, G. Louis, C. Ykman-Couvreur","doi":"10.1109/EDAC.1991.206359","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206359","url":null,"abstract":"PHIFACT is a program to synthesize combinational blocks for performance. This is mainly achieved by design space exploration at logic level. The basic multi-level architecture of the block is gradually constructed during a Boolean phase, where look ahead tools guarantee optimality. During a subsequent local restructuring phase, optimal circuits scattered in subregions of the design space are explored and selected. This is mainly based on a steepest descent method in various directions. Consequently either the complete design space, or selected subregions can be examined. Both progresses are intimately connected, placing PHIFACT in the forefront of logic synthesis tools for performance.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115798700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance macromodelling and optimization of regular VLSI structures 规则VLSI结构的性能宏观建模与优化
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206380
P. Hallam, T. I. Pritchard, G. C. Townsend
{"title":"Performance macromodelling and optimization of regular VLSI structures","authors":"P. Hallam, T. I. Pritchard, G. C. Townsend","doi":"10.1109/EDAC.1991.206380","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206380","url":null,"abstract":"The objective of this work was to develop an environment for the automated performance optimization of regular VLSI structures. The environment should enable designers with little or no knowledge of optimization theory or IC design technology to specify, create and optimize the performance of regular VLSI structures. The SRAM was initially used as the regular VLSI structure with which to develop such an environment. Macromodelling was used to increase the level of design abstraction at which the performance of a VLSI structure could be specified and new accurate, fast performance models developed. A novel numerical optimization technique which enabled a weighted sum formulations to search nonconvex design surfaces was then developed and shown to be applicable to IC performance optimization in general. Several different SRAM designs were then used to demonstrate the effectiveness and efficiency of the macromodels and optimizing environment.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124832117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Address generation for array access based on modulus m counters 基于模数计数器的数组访问地址生成
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206373
D. M. Grant, P. Denyer
{"title":"Address generation for array access based on modulus m counters","authors":"D. M. Grant, P. Denyer","doi":"10.1109/EDAC.1991.206373","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206373","url":null,"abstract":"The necessary task of address generation for RAM and ROM accesses can often result in hardware taking up an appreciable fraction of the area of a data processing IC. Close examination of the address sequences can reveal symmetry which may be exploited to automatically devise small and simple address generators, based on counters. The authors describe automated techniques used to recognise and develop symmetries in address sequences, and to synthesise the necessary address generation hardware.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122768348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Circuit partitioning for waveform relaxation 波形松弛的电路划分
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206379
W. John, W. Rissiek, K. Paap
{"title":"Circuit partitioning for waveform relaxation","authors":"W. John, W. Rissiek, K. Paap","doi":"10.1109/EDAC.1991.206379","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206379","url":null,"abstract":"New partitioning strategies for the simulation of bipolar circuits using the waveform relaxation method are presented. On the one hand concepts known from layout-generation and node tearing simulation are used. On the other hand the hierarchical structure of the circuit description list and a minimal-cut criterion is used to find a good partitioning. With the help of these new partitioning algorithms it is possible for the first time to simulate large bipolar circuits using waveform relaxation. The applicability of the algorithms is demonstrated by the simulation of real-life circuits.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128835623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Towards optimizing global mincut partitioning 优化全局最小分割
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206383
A. Hoffmann
{"title":"Towards optimizing global mincut partitioning","authors":"A. Hoffmann","doi":"10.1109/EDAC.1991.206383","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206383","url":null,"abstract":"Mincut algorithms have received much attention in the past for treating the placement problem in layout synthesis. The paper introduces a new class of mincut partitioning algorithms (SQP) meeting global minimization requirements. The new class of algorithms in its different variations is empirically compared with the classical mincut procedures as well as with recent extensions. The new algorithms have shown a significant (10 to 40%) improvement in the overall netlength compared with known algorithms. Moreover, the new class of algorithms is proved to have a linear time complexity.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122449868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Verification of synthesized circuits at register transfer level with flow graphs 用流程图验证寄存器传输级的合成电路
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206351
F. Feldbusch, Ramayya Kumar
{"title":"Verification of synthesized circuits at register transfer level with flow graphs","authors":"F. Feldbusch, Ramayya Kumar","doi":"10.1109/EDAC.1991.206351","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206351","url":null,"abstract":"Presents a new approach to the verification of automatically synthesized register transfer structures. Horizontal verification is performed on the flow graph which is largely a syntax independent representation of behavior. After extracting a flow graph from the register transfer structure by symbolic simulation, the extracted and the specified flow graphs are normalized into a normal form. A comparison of the normalized flow graphs gives the proof of correctness. The various synthesis steps have been classified into five classes and the normalization procedures have been evaluated.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125344209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis 二元决策图的变量排序在多层次逻辑综合中的应用
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206358
M. Fujita, Y. Matsunaga, Taeko Kakuda
{"title":"On variable ordering of binary decision diagrams for the application of multi-level logic synthesis","authors":"M. Fujita, Y. Matsunaga, Taeko Kakuda","doi":"10.1109/EDAC.1991.206358","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206358","url":null,"abstract":"Develops multi-level logic minimization programs using binary decision diagram (BDD). The authors present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"29 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130376407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 275
Switch and logic-level modeling in EDIF 2 0 0: limitations and proposed solutions EDIF 2.0中的开关和逻辑级建模:限制和建议的解决方案
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206445
Shankar R. Mukherjee, Maqsoodul Mannan
{"title":"Switch and logic-level modeling in EDIF 2 0 0: limitations and proposed solutions","authors":"Shankar R. Mukherjee, Maqsoodul Mannan","doi":"10.1109/EDAC.1991.206445","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206445","url":null,"abstract":"In order to transfer switch and gate-level descriptions from one simulation environment to another, information like connectivity, delay, and strength needs to be maintained. Since EDIF is rapidly becoming an industry standard, it can be used as an intermediate format for such transfers. This paper illustrates the effectiveness of EDIF 2 0 0 netlist and logic model views for this purpose and identifies its limitations. Several EDIF writers have been implemented using these concepts. In addition, this paper discusses possible extensions to improve the expressiveness of EDIF.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128285620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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