{"title":"闸门模块生成集成布局系统","authors":"P. Duchene, M. Declercq, S. M. Kang","doi":"10.1109/EDAC.1991.206398","DOIUrl":null,"url":null,"abstract":"Presents a sea-of-gates layout system able to design medium-size logic circuits in a true channelless fashion. The methodology relies on flexible leaf cell generation, systematic cell terminal abutment, a global routine scheme using integer linear programming methods, and a step-wise compaction-rerouting refinement. Modules up to several hundred transistors have been laid out compactly with more than 80% transistor utilization with two layers of metal. With top-down hierarchy, those modules can be used as macrocells.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"An integrated layout system for sea-of-gates module generation\",\"authors\":\"P. Duchene, M. Declercq, S. M. Kang\",\"doi\":\"10.1109/EDAC.1991.206398\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Presents a sea-of-gates layout system able to design medium-size logic circuits in a true channelless fashion. The methodology relies on flexible leaf cell generation, systematic cell terminal abutment, a global routine scheme using integer linear programming methods, and a step-wise compaction-rerouting refinement. Modules up to several hundred transistors have been laid out compactly with more than 80% transistor utilization with two layers of metal. With top-down hierarchy, those modules can be used as macrocells.<<ETX>>\",\"PeriodicalId\":425087,\"journal\":{\"name\":\"Proceedings of the European Conference on Design Automation.\",\"volume\":\"71 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-02-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the European Conference on Design Automation.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAC.1991.206398\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the European Conference on Design Automation.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1991.206398","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An integrated layout system for sea-of-gates module generation
Presents a sea-of-gates layout system able to design medium-size logic circuits in a true channelless fashion. The methodology relies on flexible leaf cell generation, systematic cell terminal abutment, a global routine scheme using integer linear programming methods, and a step-wise compaction-rerouting refinement. Modules up to several hundred transistors have been laid out compactly with more than 80% transistor utilization with two layers of metal. With top-down hierarchy, those modules can be used as macrocells.<>
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